/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * Copyright (C) 2012-2014, 2018, 2020-2024 Intel Corporation * Copyright (C) 2013-2015 Intel Mobile Communications GmbH * Copyright (C) 2016-2017 Intel Deutschland GmbH */ #ifndef __iwl_fw_api_phy_ctxt_h__ #define __iwl_fw_api_phy_ctxt_h__ /* Supported bands */ #define PHY_BAND_5 … #define PHY_BAND_24 … #define PHY_BAND_6 … /* Supported channel width, vary if there is VHT support */ #define IWL_PHY_CHANNEL_MODE20 … #define IWL_PHY_CHANNEL_MODE40 … #define IWL_PHY_CHANNEL_MODE80 … #define IWL_PHY_CHANNEL_MODE160 … /* and 320 MHz for EHT */ #define IWL_PHY_CHANNEL_MODE320 … /* * Control channel position: * For legacy set bit means upper channel, otherwise lower. * For VHT - bit-2 marks if the control is lower/upper relative to center-freq * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. * For EHT - bit-3 is used for extended distance * center_freq * | * 40Mhz |____|____| * 80Mhz |____|____|____|____| * 160Mhz |____|____|____|____|____|____|____|____| * 320MHz |____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|____| * code 1011 1010 1001 1000 0011 0010 0001 0000 0100 0101 0110 0111 1100 1101 1110 1111 */ #define IWL_PHY_CTRL_POS_ABOVE … #define IWL_PHY_CTRL_POS_OFFS_EXT … #define IWL_PHY_CTRL_POS_OFFS_MSK … /* * struct iwl_fw_channel_info_v1 - channel information * * @band: PHY_BAND_* * @channel: channel number * @width: PHY_[VHT|LEGACY]_CHANNEL_* * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* */ struct iwl_fw_channel_info_v1 { … } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */ /* * struct iwl_fw_channel_info - channel information * * @channel: channel number * @band: PHY_BAND_* * @width: PHY_[VHT|LEGACY]_CHANNEL_* * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* * @reserved: for future use and alignment */ struct iwl_fw_channel_info { … } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */ #define PHY_RX_CHAIN_DRIVER_FORCE_POS … #define PHY_RX_CHAIN_DRIVER_FORCE_MSK … #define PHY_RX_CHAIN_VALID_POS … #define PHY_RX_CHAIN_VALID_MSK … #define PHY_RX_CHAIN_FORCE_SEL_POS … #define PHY_RX_CHAIN_FORCE_SEL_MSK … #define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS … #define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK … #define PHY_RX_CHAIN_CNT_POS … #define PHY_RX_CHAIN_CNT_MSK … #define PHY_RX_CHAIN_MIMO_CNT_POS … #define PHY_RX_CHAIN_MIMO_CNT_MSK … #define PHY_RX_CHAIN_MIMO_FORCE_POS … #define PHY_RX_CHAIN_MIMO_FORCE_MSK … /* TODO: fix the value, make it depend on firmware at runtime? */ #define NUM_PHY_CTX … /* TODO: complete missing documentation */ /** * struct iwl_phy_context_cmd_tail - tail of iwl_phy_ctx_cmd for alignment with * various channel structures. * * @txchain_info: ??? * @rxchain_info: ??? * @acquisition_data: ??? * @dsp_cfg_flags: set to 0 */ struct iwl_phy_context_cmd_tail { … } __packed; /** * struct iwl_phy_context_cmd_v1 - config of the PHY context * ( PHY_CONTEXT_CMD = 0x8 ) * @id_and_color: ID and color of the relevant Binding * @action: action to perform, see &enum iwl_ctxt_action * @apply_time: 0 means immediate apply and context switch. * other value means apply new params after X usecs * @tx_param_color: ??? * @ci: channel info * @tail: command tail */ struct iwl_phy_context_cmd_v1 { … } __packed; /* PHY_CONTEXT_CMD_API_VER_1 */ /** * struct iwl_phy_context_cmd - config of the PHY context * ( PHY_CONTEXT_CMD = 0x8 ) * @id_and_color: ID and color of the relevant Binding * @action: action to perform, see &enum iwl_ctxt_action * @lmac_id: the lmac id the phy context belongs to * @ci: channel info * @rxchain_info: ??? * @sbb_bandwidth: 0 disabled, 1 - 40Mhz ... 4 - 320MHz * @sbb_ctrl_channel_loc: location of the control channel * @puncture_mask: bitmap of punctured subchannels * @dsp_cfg_flags: set to 0 * @reserved: reserved to align to 64 bit */ struct iwl_phy_context_cmd { … } __packed; /* PHY_CONTEXT_CMD_API_VER_3, * PHY_CONTEXT_CMD_API_VER_4, * PHY_CONTEXT_CMD_API_VER_5, * PHY_CONTEXT_CMD_API_VER_6 */ #endif /* __iwl_fw_api_phy_ctxt_h__ */
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