/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * linux/drivers/net/wireless/libertas/if_spi.c * * Driver for Marvell SPI WLAN cards. * * Copyright 2008 Analog Devices Inc. * * Authors: * Andrey Yurovsky <[email protected]> * Colin McCabe <[email protected]> */ #ifndef _LBS_IF_SPI_H_ #define _LBS_IF_SPI_H_ #define IPFIELD_ALIGN_OFFSET … #define IF_SPI_CMD_BUF_SIZE … /***************** Firmware *****************/ #define IF_SPI_FW_NAME_MAX … #define MAX_MAIN_FW_LOAD_CRC_ERR … /* Chunk size when loading the helper firmware */ #define HELPER_FW_LOAD_CHUNK_SZ … /* Value to write to indicate end of helper firmware dnld */ #define FIRMWARE_DNLD_OK … /* Value to check once the main firmware is downloaded */ #define SUCCESSFUL_FW_DOWNLOAD_MAGIC … /***************** SPI Interface Unit *****************/ /* Masks used in SPI register read/write operations */ #define IF_SPI_READ_OPERATION_MASK … #define IF_SPI_WRITE_OPERATION_MASK … /* SPI register offsets. 4-byte aligned. */ #define IF_SPI_DEVICEID_CTRL_REG … #define IF_SPI_IO_READBASE_REG … #define IF_SPI_IO_WRITEBASE_REG … #define IF_SPI_IO_RDWRPORT_REG … #define IF_SPI_CMD_READBASE_REG … #define IF_SPI_CMD_WRITEBASE_REG … #define IF_SPI_CMD_RDWRPORT_REG … #define IF_SPI_DATA_READBASE_REG … #define IF_SPI_DATA_WRITEBASE_REG … #define IF_SPI_DATA_RDWRPORT_REG … #define IF_SPI_SCRATCH_1_REG … #define IF_SPI_SCRATCH_2_REG … #define IF_SPI_SCRATCH_3_REG … #define IF_SPI_SCRATCH_4_REG … #define IF_SPI_TX_FRAME_SEQ_NUM_REG … #define IF_SPI_TX_FRAME_STATUS_REG … #define IF_SPI_HOST_INT_CTRL_REG … #define IF_SPI_CARD_INT_CAUSE_REG … #define IF_SPI_CARD_INT_STATUS_REG … #define IF_SPI_CARD_INT_EVENT_MASK_REG … #define IF_SPI_CARD_INT_STATUS_MASK_REG … #define IF_SPI_CARD_INT_RESET_SELECT_REG … #define IF_SPI_HOST_INT_CAUSE_REG … #define IF_SPI_HOST_INT_STATUS_REG … #define IF_SPI_HOST_INT_EVENT_MASK_REG … #define IF_SPI_HOST_INT_STATUS_MASK_REG … #define IF_SPI_HOST_INT_RESET_SELECT_REG … #define IF_SPI_DELAY_READ_REG … #define IF_SPI_SPU_BUS_MODE_REG … /***************** IF_SPI_DEVICEID_CTRL_REG *****************/ #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) … #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) … /***************** IF_SPI_HOST_INT_CTRL_REG *****************/ /* Host Interrupt Control bit : Wake up */ #define IF_SPI_HICT_WAKE_UP … /* Host Interrupt Control bit : WLAN ready */ #define IF_SPI_HICT_WLAN_READY … /*#define IF_SPI_HICT_FIFO_FIRST_HALF_EMPTY (1<<2) */ /*#define IF_SPI_HICT_FIFO_SECOND_HALF_EMPTY (1<<3) */ /*#define IF_SPI_HICT_IRQSRC_WLAN (1<<4) */ /* Host Interrupt Control bit : Tx auto download */ #define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO … /* Host Interrupt Control bit : Rx auto upload */ #define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO … /* Host Interrupt Control bit : Command auto download */ #define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO … /* Host Interrupt Control bit : Command auto upload */ #define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO … /***************** IF_SPI_CARD_INT_CAUSE_REG *****************/ /* Card Interrupt Case bit : Tx download over */ #define IF_SPI_CIC_TX_DOWNLOAD_OVER … /* Card Interrupt Case bit : Rx upload over */ #define IF_SPI_CIC_RX_UPLOAD_OVER … /* Card Interrupt Case bit : Command download over */ #define IF_SPI_CIC_CMD_DOWNLOAD_OVER … /* Card Interrupt Case bit : Host event */ #define IF_SPI_CIC_HOST_EVENT … /* Card Interrupt Case bit : Command upload over */ #define IF_SPI_CIC_CMD_UPLOAD_OVER … /* Card Interrupt Case bit : Power down */ #define IF_SPI_CIC_POWER_DOWN … /***************** IF_SPI_CARD_INT_STATUS_REG *****************/ #define IF_SPI_CIS_TX_DOWNLOAD_OVER … #define IF_SPI_CIS_RX_UPLOAD_OVER … #define IF_SPI_CIS_CMD_DOWNLOAD_OVER … #define IF_SPI_CIS_HOST_EVENT … #define IF_SPI_CIS_CMD_UPLOAD_OVER … #define IF_SPI_CIS_POWER_DOWN … /***************** IF_SPI_HOST_INT_CAUSE_REG *****************/ #define IF_SPI_HICU_TX_DOWNLOAD_RDY … #define IF_SPI_HICU_RX_UPLOAD_RDY … #define IF_SPI_HICU_CMD_DOWNLOAD_RDY … #define IF_SPI_HICU_CARD_EVENT … #define IF_SPI_HICU_CMD_UPLOAD_RDY … #define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW … #define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW … #define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW … #define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW … #define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW … #define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW … /***************** IF_SPI_HOST_INT_STATUS_REG *****************/ /* Host Interrupt Status bit : Tx download ready */ #define IF_SPI_HIST_TX_DOWNLOAD_RDY … /* Host Interrupt Status bit : Rx upload ready */ #define IF_SPI_HIST_RX_UPLOAD_RDY … /* Host Interrupt Status bit : Command download ready */ #define IF_SPI_HIST_CMD_DOWNLOAD_RDY … /* Host Interrupt Status bit : Card event */ #define IF_SPI_HIST_CARD_EVENT … /* Host Interrupt Status bit : Command upload ready */ #define IF_SPI_HIST_CMD_UPLOAD_RDY … /* Host Interrupt Status bit : I/O write FIFO overflow */ #define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW … /* Host Interrupt Status bit : I/O read FIFO underflow */ #define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW … /* Host Interrupt Status bit : Data write FIFO overflow */ #define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW … /* Host Interrupt Status bit : Data read FIFO underflow */ #define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW … /* Host Interrupt Status bit : Command write FIFO overflow */ #define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW … /* Host Interrupt Status bit : Command read FIFO underflow */ #define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW … /***************** IF_SPI_HOST_INT_STATUS_MASK_REG *****************/ /* Host Interrupt Status Mask bit : Tx download ready */ #define IF_SPI_HISM_TX_DOWNLOAD_RDY … /* Host Interrupt Status Mask bit : Rx upload ready */ #define IF_SPI_HISM_RX_UPLOAD_RDY … /* Host Interrupt Status Mask bit : Command download ready */ #define IF_SPI_HISM_CMD_DOWNLOAD_RDY … /* Host Interrupt Status Mask bit : Card event */ #define IF_SPI_HISM_CARDEVENT … /* Host Interrupt Status Mask bit : Command upload ready */ #define IF_SPI_HISM_CMD_UPLOAD_RDY … /* Host Interrupt Status Mask bit : I/O write FIFO overflow */ #define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW … /* Host Interrupt Status Mask bit : I/O read FIFO underflow */ #define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW … /* Host Interrupt Status Mask bit : Data write FIFO overflow */ #define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW … /* Host Interrupt Status Mask bit : Data write FIFO underflow */ #define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW … /* Host Interrupt Status Mask bit : Command write FIFO overflow */ #define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW … /* Host Interrupt Status Mask bit : Command write FIFO underflow */ #define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW … /***************** IF_SPI_SPU_BUS_MODE_REG *****************/ /* SCK edge on which the WLAN module outputs data on MISO */ #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING … #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING … /* In a SPU read operation, there is a delay between writing the SPU * register name and getting back data from the WLAN module. * This can be specified in terms of nanoseconds or in terms of dummy * clock cycles which the master must output before receiving a response. */ #define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK … #define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED … /* Some different modes of SPI operation */ #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA … #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA … #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA … #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA … #endif
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