/* SPDX-License-Identifier: GPL-2.0-only */ /* * NXP Wireless LAN device driver: SDIO specific definitions * * Copyright 2011-2020 NXP */ #ifndef _MWIFIEX_SDIO_H #define _MWIFIEX_SDIO_H #include <linux/completion.h> #include <linux/mmc/sdio.h> #include <linux/mmc/sdio_ids.h> #include <linux/mmc/sdio_func.h> #include <linux/mmc/card.h> #include <linux/mmc/host.h> #include "main.h" #define SD8786_DEFAULT_FW_NAME … #define SD8787_DEFAULT_FW_NAME … #define SD8797_DEFAULT_FW_NAME … #define SD8897_DEFAULT_FW_NAME … #define SD8887_DEFAULT_FW_NAME … #define SD8801_DEFAULT_FW_NAME … #define SD8977_DEFAULT_FW_NAME … #define SD8978_SDIOUART_FW_NAME … #define SD8987_DEFAULT_FW_NAME … #define SD8997_DEFAULT_FW_NAME … #define SD8997_SDIOUART_FW_NAME … #define BLOCK_MODE … #define BYTE_MODE … #define MWIFIEX_SDIO_IO_PORT_MASK … #define MWIFIEX_SDIO_BYTE_MODE_MASK … #define MWIFIEX_MAX_FUNC2_REG_NUM … #define MWIFIEX_SDIO_SCRATCH_SIZE … #define SDIO_MPA_ADDR_BASE … #define CTRL_PORT … #define CTRL_PORT_MASK … #define CMD_PORT_UPLD_INT_MASK … #define CMD_PORT_DNLD_INT_MASK … #define HOST_TERM_CMD53 … #define REG_PORT … #define MEM_PORT … #define CMD53_NEW_MODE … #define CMD_PORT_RD_LEN_EN … #define CMD_PORT_AUTO_EN … #define CMD_PORT_SLCT … #define UP_LD_CMD_PORT_HOST_INT_STATUS … #define DN_LD_CMD_PORT_HOST_INT_STATUS … #define MWIFIEX_MP_AGGR_BUF_SIZE_16K … #define MWIFIEX_MP_AGGR_BUF_SIZE_32K … /* we leave one block of 256 bytes for DMA alignment*/ #define MWIFIEX_MP_AGGR_BUF_SIZE_MAX … /* Misc. Config Register : Auto Re-enable interrupts */ #define AUTO_RE_ENABLE_INT … /* Host Control Registers : Configuration */ #define CONFIGURATION_REG … /* Host Control Registers : Host power up */ #define HOST_POWER_UP … /* Host Control Registers : Upload host interrupt mask */ #define UP_LD_HOST_INT_MASK … /* Host Control Registers : Download host interrupt mask */ #define DN_LD_HOST_INT_MASK … /* Host Control Registers : Upload host interrupt status */ #define UP_LD_HOST_INT_STATUS … /* Host Control Registers : Download host interrupt status */ #define DN_LD_HOST_INT_STATUS … /* Host Control Registers : Host interrupt status */ #define CARD_INT_STATUS_REG … /* Card Control Registers : Card I/O ready */ #define CARD_IO_READY … /* Card Control Registers : Download card ready */ #define DN_LD_CARD_RDY … /* Max retry number of CMD53 write */ #define MAX_WRITE_IOMEM_RETRY … /* SDIO Tx aggregation in progress ? */ #define MP_TX_AGGR_IN_PROGRESS(a) … /* SDIO Tx aggregation buffer room for next packet ? */ #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) … /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */ #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) … /* SDIO Tx aggregation limit ? */ #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) … /* Reset SDIO Tx aggregation buffer parameters */ #define MP_TX_AGGR_BUF_RESET(a) … /* SDIO Rx aggregation limit ? */ #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) … /* SDIO Rx aggregation in progress ? */ #define MP_RX_AGGR_IN_PROGRESS(a) … /* SDIO Rx aggregation buffer room for next packet ? */ #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) … /* Reset SDIO Rx aggregation buffer parameters */ #define MP_RX_AGGR_BUF_RESET(a) … /* data structure for SDIO MPA TX */ struct mwifiex_sdio_mpa_tx { … }; struct mwifiex_sdio_mpa_rx { … }; int mwifiex_bus_register(void); void mwifiex_bus_unregister(void); struct mwifiex_sdio_card_reg { … }; struct sdio_mmc_card { … }; struct mwifiex_sdio_device { … }; /* * .cmdrsp_complete handler */ static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter, struct sk_buff *skb) { … } /* * .event_complete handler */ static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter, struct sk_buff *skb) { … } static inline bool mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card) { … } static inline bool mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card) { … } /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */ static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card, u16 rx_len, u8 port) { … } #endif /* _MWIFIEX_SDIO_H */
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