/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2014 Felix Fietkau <[email protected]> * Copyright (C) 2015 Jakub Kicinski <[email protected]> */ #ifndef MT7601U_H #define MT7601U_H #include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/device.h> #include <linux/mutex.h> #include <linux/usb.h> #include <linux/completion.h> #include <net/mac80211.h> #include <linux/debugfs.h> #include <linux/average.h> #include "regs.h" #define MT_CALIBRATE_INTERVAL … #define MT_FREQ_CAL_INIT_DELAY … #define MT_FREQ_CAL_CHECK_INTERVAL … #define MT_FREQ_CAL_ADJ_INTERVAL … #define MT_BBP_REG_VERSION … #define MT_USB_AGGR_SIZE_LIMIT … #define MT_USB_AGGR_TIMEOUT … #define MT_RX_ORDER … #define MT_RX_URB_SIZE … struct mt7601u_dma_buf { … }; struct mt7601u_mcu { … }; struct mt7601u_freq_cal { … }; struct mac_stats { … }; #define N_RX_ENTRIES … struct mt7601u_rx_queue { … }; #define N_TX_ENTRIES … struct mt7601u_tx_queue { … }; /* WCID allocation: * 0: mcast wcid * 1: bssid wcid * 1...: STAs * ...7e: group wcids * 7f: reserved */ #define N_WCIDS … #define GROUP_WCID(idx) … struct mt7601u_eeprom_params; #define MT_EE_TEMPERATURE_SLOPE … #define MT_FREQ_OFFSET_INVALID … enum mt_temp_mode { … }; enum mt_bw { … }; enum { … }; DECLARE_EWMA(rssi, 10, 4); /** * struct mt7601u_dev - adapter structure * @lock: protects @wcid->tx_rate. * @mac_lock: locks out mac80211's tx status and rx paths. * @tx_lock: protects @tx_q and changes of MT7601U_STATE_*_STATS * flags in @state. * @rx_lock: protects @rx_q. * @con_mon_lock: protects @ap_bssid, @bcn_*, @avg_rssi. * @mutex: ensures exclusive access from mac80211 callbacks. * @vendor_req_mutex: protects @vend_buf, ensures atomicity of read/write * accesses * @reg_atomic_mutex: ensures atomicity of indirect register accesses * (accesses to RF and BBP). * @hw_atomic_mutex: ensures exclusive access to HW during critical * operations (power management, channel switch). */ struct mt7601u_dev { … }; struct mt7601u_tssi_params { … }; struct mt76_wcid { … }; struct mt76_vif { … }; struct mt76_sta { … }; struct mt76_reg_pair { … }; struct mt7601u_rxwi; extern const struct ieee80211_ops mt7601u_ops; void mt7601u_init_debugfs(struct mt7601u_dev *dev); u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset); void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val); u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); void mt7601u_wr_copy(struct mt7601u_dev *dev, u32 offset, const void *data, int len); int mt7601u_wait_asic_ready(struct mt7601u_dev *dev); bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, int timeout); bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, int timeout); /* Compatibility with mt76 */ #define mt76_rmw_field(_dev, _reg, _field, _val) … static inline u32 mt76_rr(struct mt7601u_dev *dev, u32 offset) { … } static inline void mt76_wr(struct mt7601u_dev *dev, u32 offset, u32 val) { … } static inline u32 mt76_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) { … } static inline u32 mt76_set(struct mt7601u_dev *dev, u32 offset, u32 val) { … } static inline u32 mt76_clear(struct mt7601u_dev *dev, u32 offset, u32 val) { … } int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base, const struct mt76_reg_pair *data, int len); int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset, const u32 *data, int n); void mt7601u_addr_wr(struct mt7601u_dev *dev, const u32 offset, const u8 *addr); /* Init */ struct mt7601u_dev *mt7601u_alloc_device(struct device *dev); int mt7601u_init_hardware(struct mt7601u_dev *dev); int mt7601u_register_device(struct mt7601u_dev *dev); void mt7601u_cleanup(struct mt7601u_dev *dev); int mt7601u_mac_start(struct mt7601u_dev *dev); void mt7601u_mac_stop(struct mt7601u_dev *dev); /* PHY */ int mt7601u_phy_init(struct mt7601u_dev *dev); int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev); void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path); void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 path); int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw); void mt7601u_agc_save(struct mt7601u_dev *dev); void mt7601u_agc_restore(struct mt7601u_dev *dev); int mt7601u_phy_set_channel(struct mt7601u_dev *dev, struct cfg80211_chan_def *chandef); void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev); int mt7601u_phy_get_rssi(struct mt7601u_dev *dev, struct mt7601u_rxwi *rxwi, u16 rate); void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev, struct ieee80211_bss_conf *info); /* MAC */ void mt7601u_mac_work(struct work_struct *work); void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot, int ht_mode); void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb); void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval); void mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac); void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev); /* TX */ void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb); int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, unsigned int link_id, u16 queue, const struct ieee80211_tx_queue_params *params); void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb); void mt7601u_tx_stat(struct work_struct *work); /* util */ void mt76_remove_hdr_pad(struct sk_buff *skb); int mt76_insert_hdr_pad(struct sk_buff *skb); u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below); static inline u32 mt7601u_mac_set_ctrlch(struct mt7601u_dev *dev, bool below) { … } int mt7601u_dma_init(struct mt7601u_dev *dev); void mt7601u_dma_cleanup(struct mt7601u_dev *dev); int mt7601u_dma_enqueue_tx(struct mt7601u_dev *dev, struct sk_buff *skb, struct mt76_wcid *wcid, int hw_q); #endif
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