/* SPDX-License-Identifier: ISC */ /* Copyright (C) 2020 MediaTek Inc. */ #ifndef __MT7915_REGS_H #define __MT7915_REGS_H /* used to differentiate between generations */ struct mt7915_reg_desc { … }; enum reg_rev { … }; enum offs_rev { … }; #define __REG(id) … #define __OFFS(id) … /* MCU WFDMA0 */ #define MT_MCU_WFDMA0_BASE … #define MT_MCU_WFDMA0(ofs) … #define MT_MCU_WFDMA0_DUMMY_CR … /* MCU WFDMA1 */ #define MT_MCU_WFDMA1_BASE … #define MT_MCU_WFDMA1(ofs) … #define MT_MCU_INT_EVENT … #define MT_MCU_INT_EVENT_DMA_STOPPED … #define MT_MCU_INT_EVENT_DMA_INIT … #define MT_MCU_INT_EVENT_SER_TRIGGER … #define MT_MCU_INT_EVENT_RESET_DONE … /* PLE */ #define MT_PLE_BASE … #define MT_PLE(ofs) … #define MT_PLE_HOST_RPT0 … #define MT_PLE_HOST_RPT0_TX_LATENCY … #define MT_FL_Q_EMPTY … #define MT_FL_Q0_CTRL … #define MT_FL_Q2_CTRL … #define MT_FL_Q3_CTRL … #define MT_PLE_FREEPG_CNT … #define MT_PLE_FREEPG_HEAD_TAIL … #define MT_PLE_PG_HIF_GROUP … #define MT_PLE_HIF_PG_INFO … #define MT_PLE_AC_QEMPTY(ac, n) … #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) … #define MT_PSE_BASE … #define MT_PSE(ofs) … /* WF MDP TOP */ #define MT_MDP_BASE … #define MT_MDP(ofs) … #define MT_MDP_DCR0 … #define MT_MDP_DCR0_DAMSDU_EN … #define MT_MDP_DCR0_RX_HDR_TRANS_EN … #define MT_MDP_DCR1 … #define MT_MDP_DCR1_MAX_RX_LEN … #define MT_MDP_DCR2 … #define MT_MDP_DCR2_RX_TRANS_SHORT … #define MT_MDP_BNRCFR0(_band) … #define MT_MDP_RCFR0_MCU_RX_MGMT … #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR … #define MT_MDP_RCFR0_MCU_RX_CTL_BAR … #define MT_MDP_BNRCFR1(_band) … #define MT_MDP_RCFR1_MCU_RX_BYPASS … #define MT_MDP_RCFR1_RX_DROPPED_UCAST … #define MT_MDP_RCFR1_RX_DROPPED_MCAST … #define MT_MDP_TO_HIF … #define MT_MDP_TO_WM … /* TRB: band 0(0x820e1000), band 1(0x820f1000) */ #define MT_WF_TRB_BASE(_band) … #define MT_WF_TRB(_band, ofs) … #define MT_TRB_RXPSR0(_band) … #define MT_TRB_RXPSR0_RX_WTBL_PTR … #define MT_TRB_RXPSR0_RX_RMAC_PTR … /* TMAC: band 0(0x820e4000), band 1(0x820f4000) */ #define MT_WF_TMAC_BASE(_band) … #define MT_WF_TMAC(_band, ofs) … #define MT_TMAC_TCR0(_band) … #define MT_TMAC_TCR0_TX_BLINK … #define MT_TMAC_TCR0_TBTT_STOP_CTRL … #define MT_TMAC_CDTR(_band) … #define MT_TMAC_ODTR(_band) … #define MT_TIMEOUT_VAL_PLCP … #define MT_TIMEOUT_VAL_CCA … #define MT_TMAC_ATCR(_band) … #define MT_TMAC_ATCR_TXV_TOUT … #define MT_TMAC_TRCR0(_band) … #define MT_TMAC_TRCR0_TR2T_CHK … #define MT_TMAC_TRCR0_I2T_CHK … #define MT_TMAC_ICR0(_band) … #define MT_IFS_EIFS_OFDM … #define MT_IFS_RIFS … #define MT_IFS_SIFS … #define MT_IFS_SLOT … #define MT_TMAC_ICR1(_band) … #define MT_IFS_EIFS_CCK … #define MT_TMAC_CTCR0(_band) … #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME … #define MT_TMAC_CTCR0_INS_DDLMT_EN … #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN … #define MT_TMAC_TFCR0(_band) … /* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */ #define MT_WF_DMA_BASE(_band) … #define MT_WF_DMA(_band, ofs) … #define MT_DMA_DCR0(_band) … #define MT_DMA_DCR0_MAX_RX_LEN … #define MT_DMA_DCR0_RXD_G5_EN … /* WTBLOFF TOP: band 0(0x820e9000),band 1(0x820f9000) */ #define MT_WTBLOFF_TOP_BASE(_band) … #define MT_WTBLOFF_TOP(_band, ofs) … #define MT_WTBLOFF_TOP_RSCR(_band) … #define MT_WTBLOFF_TOP_RSCR_RCPI_MODE … #define MT_WTBLOFF_TOP_RSCR_RCPI_PARAM … /* ETBF: band 0(0x820ea000), band 1(0x820fa000) */ #define MT_WF_ETBF_BASE(_band) … #define MT_WF_ETBF(_band, ofs) … #define MT_ETBF_TX_NDP_BFRP(_band) … #define MT_ETBF_TX_FB_CPL … #define MT_ETBF_TX_FB_TRI … #define MT_ETBF_PAR_RPT0(_band) … #define MT_ETBF_PAR_RPT0_FB_BW … #define MT_ETBF_PAR_RPT0_FB_NC … #define MT_ETBF_PAR_RPT0_FB_NR … #define MT_ETBF_TX_APP_CNT(_band) … #define MT_ETBF_TX_IBF_CNT … #define MT_ETBF_TX_EBF_CNT … #define MT_ETBF_RX_FB_CNT(_band) … #define MT_ETBF_RX_FB_ALL … #define MT_ETBF_RX_FB_HE … #define MT_ETBF_RX_FB_VHT … #define MT_ETBF_RX_FB_HT … /* LPON: band 0(0x820eb000), band 1(0x820fb000) */ #define MT_WF_LPON_BASE(_band) … #define MT_WF_LPON(_band, ofs) … #define MT_LPON_UTTR0(_band) … #define MT_LPON_UTTR1(_band) … #define MT_LPON_FRCR(_band) … #define MT_LPON_TCR(_band, n) … #define MT_LPON_TCR_MT7916(_band, n) … #define MT_LPON_TCR_SW_MODE … #define MT_LPON_TCR_SW_WRITE … #define MT_LPON_TCR_SW_ADJUST … #define MT_LPON_TCR_SW_READ … /* MIB: band 0(0x820ed000), band 1(0x820fd000) */ /* These counters are (mostly?) clear-on-read. So, some should not * be read at all in case firmware is already reading them. These * are commented with 'DNR' below. The DNR stats will be read by querying * the firmware API for the appropriate message. For counters the driver * does read, the driver should accumulate the counters. */ #define MT_WF_MIB_BASE(_band) … #define MT_WF_MIB(_band, ofs) … #define MT_MIB_SDR0(_band) … #define MT_MIB_SDR0_BERACON_TX_CNT_MASK … #define MT_MIB_SDR3(_band) … #define MT_MIB_SDR3_FCS_ERR_MASK … #define MT_MIB_SDR3_FCS_ERR_MASK_MT7916 … #define MT_MIB_SDR4(_band) … #define MT_MIB_SDR4_RX_FIFO_FULL_MASK … /* rx mpdu counter, full 32 bits */ #define MT_MIB_SDR5(_band) … #define MT_MIB_SDR6(_band) … #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK … #define MT_MIB_SDR7(_band) … #define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK … #define MT_MIB_SDR8(_band) … #define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK … /* aka CCA_NAV_TX_TIME */ #define MT_MIB_SDR9_DNR(_band) … #define MT_MIB_SDR9_CCA_BUSY_TIME_MASK … #define MT_MIB_SDR10(_band) … #define MT_MIB_SDR10_MRDY_COUNT_MASK … #define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916 … #define MT_MIB_SDR11(_band) … #define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK … /* tx ampdu cnt, full 32 bits */ #define MT_MIB_SDR12(_band) … #define MT_MIB_SDR13(_band) … #define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK … /* counts all mpdus in ampdu, regardless of success */ #define MT_MIB_SDR14(_band) … #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK … #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916 … /* counts all successfully tx'd mpdus in ampdu */ #define MT_MIB_SDR15(_band) … #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK … #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916 … /* in units of 'us' */ #define MT_MIB_SDR16(_band) … #define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK … #define MT_MIB_SDR17(_band) … #define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK … #define MT_MIB_SDR18(_band) … #define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK … /* units are us */ #define MT_MIB_SDR19(_band) … #define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK … #define MT_MIB_SDR20(_band) … #define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK … #define MT_MIB_SDR21(_band) … #define MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK … /* rx ampdu count, 32-bit */ #define MT_MIB_SDR22(_band) … /* rx ampdu bytes count, 32-bit */ #define MT_MIB_SDR23(_band) … /* rx ampdu valid subframe count */ #define MT_MIB_SDR24(_band) … #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK … #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916 … /* rx ampdu valid subframe bytes count, 32bits */ #define MT_MIB_SDR25(_band) … /* remaining windows protected stats */ #define MT_MIB_SDR27(_band) … #define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK … #define MT_MIB_SDR28(_band) … #define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK … #define MT_MIB_SDR29(_band) … #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK … #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916 … #define MT_MIB_SDRVEC(_band) … #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK … #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916 … /* rx blockack count, 32 bits */ #define MT_MIB_SDR31(_band) … #define MT_MIB_SDR32(_band) … #define MT_MIB_SDR32_TX_PKT_EBF_CNT … #define MT_MIB_SDR32_TX_PKT_IBF_CNT … #define MT_MIB_SDR33(_band) … #define MT_MIB_SDR33_TX_PKT_IBF_CNT … #define MT_MIB_SDRMUBF(_band) … #define MT_MIB_MU_BF_TX_CNT … /* 36, 37 both DNR */ #define MT_MIB_DR8(_band) … #define MT_MIB_DR9(_band) … #define MT_MIB_DR11(_band) … #define MT_MIB_MB_SDR0(_band, n) … #define MT_MIB_RTS_RETRIES_COUNT_MASK … #define MT_MIB_RTS_COUNT_MASK … #define MT_MIB_MB_SDR1(_band, n) … #define MT_MIB_BA_MISS_COUNT_MASK … #define MT_MIB_ACK_FAIL_COUNT_MASK … #define MT_MIB_MB_SDR2(_band, n) … #define MT_MIB_MB_BFTF(_band, n) … #define MT_TX_AGG_CNT(_band, n) … #define MT_TX_AGG_CNT2(_band, n) … #define MT_MIB_ARNG(_band, n) … #define MT_MIB_ARNCR_RANGE(val, n) … #define MT_MIB_BFCR0(_band) … #define MT_MIB_BFCR0_RX_FB_HT … #define MT_MIB_BFCR0_RX_FB_VHT … #define MT_MIB_BFCR1(_band) … #define MT_MIB_BFCR1_RX_FB_HE … #define MT_MIB_BFCR2(_band) … #define MT_MIB_BFCR2_BFEE_TX_FB_TRIG … #define MT_MIB_BFCR7(_band) … #define MT_MIB_BFCR7_BFEE_TX_FB_CPL … /* WTBLON TOP */ #define MT_WTBLON_TOP_BASE … #define MT_WTBLON_TOP(ofs) … #define MT_WTBLON_TOP_WDUCR … #define MT_WTBLON_TOP_WDUCR_GROUP … #define MT_WTBL_UPDATE … #define MT_WTBL_UPDATE_WLAN_IDX … #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR … #define MT_WTBL_UPDATE_BUSY … /* WTBL */ #define MT_WTBL_BASE … #define MT_WTBL_LMAC_ID … #define MT_WTBL_LMAC_DW … #define MT_WTBL_LMAC_OFFS(_id, _dw) … /* AGG: band 0(0x820e2000), band 1(0x820f2000) */ #define MT_WF_AGG_BASE(_band) … #define MT_WF_AGG(_band, ofs) … #define MT_AGG_AWSCR0(_band, _n) … #define MT_AGG_PCR0(_band, _n) … #define MT_AGG_PCR0_MM_PROT … #define MT_AGG_PCR0_GF_PROT … #define MT_AGG_PCR0_BW20_PROT … #define MT_AGG_PCR0_BW40_PROT … #define MT_AGG_PCR0_BW80_PROT … #define MT_AGG_PCR0_ERP_PROT … #define MT_AGG_PCR0_VHT_PROT … #define MT_AGG_PCR0_PTA_WIN_DIS … #define MT_AGG_PCR1_RTS0_NUM_THRES … #define MT_AGG_PCR1_RTS0_LEN_THRES … #define MT_AGG_ACR0(_band) … #define MT_AGG_ACR_CFEND_RATE … #define MT_AGG_ACR_BAR_RATE … #define MT_AGG_ACR4(_band) … #define MT_AGG_ACR_PPDU_TXS2H … #define MT_AGG_MRCR(_band) … #define MT_AGG_MRCR_BAR_CNT_LIMIT … #define MT_AGG_MRCR_LAST_RTS_CTS_RN … #define MT_AGG_MRCR_RTS_FAIL_LIMIT … #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT … #define MT_AGG_ATCR1(_band) … #define MT_AGG_ATCR3(_band) … /* ARB: band 0(0x820e3000), band 1(0x820f3000) */ #define MT_WF_ARB_BASE(_band) … #define MT_WF_ARB(_band, ofs) … #define MT_ARB_SCR(_band) … #define MT_ARB_SCR_TX_DISABLE … #define MT_ARB_SCR_RX_DISABLE … #define MT_ARB_DRNGR0(_band, _n) … /* RMAC: band 0(0x820e5000), band 1(0x820f5000) */ #define MT_WF_RMAC_BASE(_band) … #define MT_WF_RMAC(_band, ofs) … #define MT_WF_RFCR(_band) … #define MT_WF_RFCR_DROP_STBC_MULTI … #define MT_WF_RFCR_DROP_FCSFAIL … #define MT_WF_RFCR_DROP_VERSION … #define MT_WF_RFCR_DROP_PROBEREQ … #define MT_WF_RFCR_DROP_MCAST … #define MT_WF_RFCR_DROP_BCAST … #define MT_WF_RFCR_DROP_MCAST_FILTERED … #define MT_WF_RFCR_DROP_A3_MAC … #define MT_WF_RFCR_DROP_A3_BSSID … #define MT_WF_RFCR_DROP_A2_BSSID … #define MT_WF_RFCR_DROP_OTHER_BEACON … #define MT_WF_RFCR_DROP_FRAME_REPORT … #define MT_WF_RFCR_DROP_CTL_RSV … #define MT_WF_RFCR_DROP_CTS … #define MT_WF_RFCR_DROP_RTS … #define MT_WF_RFCR_DROP_DUPLICATE … #define MT_WF_RFCR_DROP_OTHER_BSS … #define MT_WF_RFCR_DROP_OTHER_UC … #define MT_WF_RFCR_DROP_OTHER_TIM … #define MT_WF_RFCR_DROP_NDPA … #define MT_WF_RFCR_DROP_UNWANTED_CTL … #define MT_WF_RFCR1(_band) … #define MT_WF_RFCR1_DROP_ACK … #define MT_WF_RFCR1_DROP_BF_POLL … #define MT_WF_RFCR1_DROP_BA … #define MT_WF_RFCR1_DROP_CFEND … #define MT_WF_RFCR1_DROP_CFACK … #define MT_WF_RMAC_RSVD0(_band) … #define MT_WF_RMAC_RSVD0_EIFS_CLR … #define MT_WF_RMAC_MIB_AIRTIME0(_band) … #define MT_WF_RMAC_MIB_RXTIME_CLR … #define MT_WF_RMAC_MIB_OBSS_BACKOFF … #define MT_WF_RMAC_MIB_ED_OFFSET … #define MT_WF_RMAC_MIB_AIRTIME1(_band) … #define MT_WF_RMAC_MIB_NONQOSD_BACKOFF … #define MT_WF_RMAC_MIB_AIRTIME3(_band) … #define MT_WF_RMAC_MIB_QOS01_BACKOFF … #define MT_WF_RMAC_MIB_AIRTIME4(_band) … #define MT_WF_RMAC_MIB_QOS23_BACKOFF … /* WFDMA0 */ #define MT_WFDMA0_BASE … #define MT_WFDMA0(ofs) … #define MT_WFDMA0_RST … #define MT_WFDMA0_RST_LOGIC_RST … #define MT_WFDMA0_RST_DMASHDL_ALL_RST … #define MT_WFDMA0_BUSY_ENA … #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 … #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 … #define MT_WFDMA0_BUSY_ENA_RX_FIFO … #define MT_WFDMA0_MCU_HOST_INT_ENA … #define MT_WFDMA0_GLO_CFG … #define MT_WFDMA0_GLO_CFG_TX_DMA_EN … #define MT_WFDMA0_GLO_CFG_RX_DMA_EN … #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO … #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO … #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 … #define MT_WFDMA0_RST_DTX_PTR … #define MT_WFDMA0_EXT0_CFG … #define MT_WFDMA0_EXT0_RXWB_KEEP … #define MT_WFDMA0_PRI_DLY_INT_CFG0 … #define MT_WFDMA0_PRI_DLY_INT_CFG1 … #define MT_WFDMA0_PRI_DLY_INT_CFG2 … #define MT_WPDMA_GLO_CFG … /* WFDMA1 */ #define MT_WFDMA1_BASE … #define MT_WFDMA1(ofs) … #define MT_WFDMA1_RST … #define MT_WFDMA1_RST_LOGIC_RST … #define MT_WFDMA1_RST_DMASHDL_ALL_RST … #define MT_WFDMA1_BUSY_ENA … #define MT_WFDMA1_BUSY_ENA_TX_FIFO0 … #define MT_WFDMA1_BUSY_ENA_TX_FIFO1 … #define MT_WFDMA1_BUSY_ENA_RX_FIFO … #define MT_WFDMA1_GLO_CFG … #define MT_WFDMA1_GLO_CFG_TX_DMA_EN … #define MT_WFDMA1_GLO_CFG_RX_DMA_EN … #define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO … #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO … #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2 … #define MT_WFDMA1_RST_DTX_PTR … #define MT_WFDMA1_PRI_DLY_INT_CFG0 … /* WFDMA CSR */ #define MT_WFDMA_EXT_CSR_BASE … #define MT_WFDMA_EXT_CSR_PHYS_BASE … #define MT_WFDMA_EXT_CSR(ofs) … #define MT_WFDMA_EXT_CSR_PHYS(ofs) … #define MT_WFDMA_HOST_CONFIG … #define MT_WFDMA_HOST_CONFIG_PDMA_BAND … #define MT_WFDMA_HOST_CONFIG_WED … #define MT_WFDMA_WED_RING_CONTROL … #define MT_WFDMA_WED_RING_CONTROL_TX0 … #define MT_WFDMA_WED_RING_CONTROL_TX1 … #define MT_WFDMA_WED_RING_CONTROL_RX1 … #define MT_WFDMA_EXT_CSR_HIF_MISC … #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY … #define MT_PCIE_RECOG_ID … #define MT_PCIE_RECOG_ID_MASK … #define MT_PCIE_RECOG_ID_SEM … #define MT_INT_WED_SOURCE_CSR … #define MT_INT_WED_MASK_CSR … #define MT_WED_TX_RING_BASE … #define MT_WED_RX_RING_BASE … /* WFDMA0 PCIE1 */ #define MT_WFDMA0_PCIE1_BASE … #define MT_WFDMA0_PCIE1(ofs) … #define MT_WFDMA0_PCIE1_BUSY_ENA … #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 … #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 … #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO … /* WFDMA1 PCIE1 */ #define MT_WFDMA1_PCIE1_BASE … #define MT_WFDMA1_PCIE1(ofs) … #define MT_WFDMA1_PCIE1_BUSY_ENA … #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 … #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 … #define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO … /* WFDMA COMMON */ #define __RXQ(q) … #define __TXQ(q) … #define MT_Q_ID(q) … #define MT_Q_BASE(q) … #define MT_MCUQ_ID(q) … #define MT_TXQ_ID(q) … #define MT_RXQ_ID(q) … #define MT_MCUQ_RING_BASE(q) … #define MT_TXQ_RING_BASE(q) … #define MT_RXQ_RING_BASE(q) … #define MT_MCUQ_EXT_CTRL(q) … #define MT_RXQ_BAND1_CTRL(q) … #define MT_TXQ_EXT_CTRL(q) … #define MT_TXQ_WED_RING_BASE … #define MT_RXQ_WED_RING_BASE … #define MT_RXQ_WED_DATA_RING_BASE … #define MT_INT_SOURCE_CSR … #define MT_INT_MASK_CSR … #define MT_INT1_SOURCE_CSR … #define MT_INT1_MASK_CSR … #define MT_INT_RX_DONE_BAND0 … #define MT_INT_RX_DONE_BAND1 … #define MT_INT_RX_DONE_WM … #define MT_INT_RX_DONE_WA … #define MT_INT_RX_DONE_WA_MAIN … #define MT_INT_RX_DONE_WA_EXT … #define MT_INT_MCU_CMD … #define MT_INT_RX_DONE_BAND0_MT7916 … #define MT_INT_RX_DONE_BAND1_MT7916 … #define MT_INT_RX_DONE_WA_MAIN_MT7916 … #define MT_INT_RX_DONE_WA_EXT_MT7916 … #define MT_INT_WED_RX_DONE_BAND0_MT7916 … #define MT_INT_WED_RX_DONE_BAND1_MT7916 … #define MT_INT_WED_RX_DONE_WA_MAIN_MT7916 … #define MT_INT_WED_RX_DONE_WA_MT7916 … #define MT_INT_RX(q) … #define MT_INT_TX_MCU(q) … #define MT_INT_RX_DONE_MCU … #define MT_INT_BAND0_RX_DONE … #define MT_INT_BAND1_RX_DONE … #define MT_INT_RX_DONE_ALL … #define MT_INT_TX_DONE_FWDL … #define MT_INT_TX_DONE_MCU_WM … #define MT_INT_TX_DONE_MCU_WA … #define MT_INT_TX_DONE_BAND0 … #define MT_INT_TX_DONE_BAND1 … #define MT_INT_TX_DONE_MCU_WA_MT7916 … #define MT_INT_WED_TX_DONE_BAND0 … #define MT_INT_WED_TX_DONE_BAND1 … #define MT_INT_TX_DONE_MCU … #define MT_MCU_CMD … #define MT_MCU_CMD_STOP_DMA_FW_RELOAD … #define MT_MCU_CMD_STOP_DMA … #define MT_MCU_CMD_RESET_DONE … #define MT_MCU_CMD_RECOVERY_DONE … #define MT_MCU_CMD_NORMAL_STATE … #define MT_MCU_CMD_ERROR_MASK … #define MT_MCU_CMD_WA_WDT … #define MT_MCU_CMD_WM_WDT … #define MT_MCU_CMD_WDT_MASK … /* TOP RGU */ #define MT_TOP_RGU_BASE … #define MT_TOP_PWR_CTRL … #define MT_TOP_PWR_KEY … #define MT_TOP_PWR_SW_RST … #define MT_TOP_PWR_SW_PWR_ON … #define MT_TOP_PWR_HW_CTRL … #define MT_TOP_PWR_PWR_ON … #define MT_TOP_RGU_SYSRAM_PDN … #define MT_TOP_RGU_SYSRAM_SLP … #define MT_TOP_WFSYS_PWR … #define MT_TOP_PWR_EN_MASK … #define MT_TOP_PWR_ACK_MASK … #define MT_TOP_PWR_KEY_MASK … #define MT7986_TOP_WM_RESET … #define MT7986_TOP_WM_RESET_MASK … /* l1/l2 remap */ #define MT_HIF_REMAP_L1 … #define MT_HIF_REMAP_L1_MT7916 … #define MT_HIF_REMAP_L1_MASK … #define MT_HIF_REMAP_L1_OFFSET … #define MT_HIF_REMAP_L1_BASE … #define MT_HIF_REMAP_BASE_L1 … #define MT_HIF_REMAP_L2 … #define MT_HIF_REMAP_L2_MASK … #define MT_HIF_REMAP_L2_OFFSET … #define MT_HIF_REMAP_L2_BASE … #define MT_HIF_REMAP_L2_MT7916 … #define MT_HIF_REMAP_L2_MASK_MT7916 … #define MT_HIF_REMAP_L2_OFFSET_MT7916 … #define MT_HIF_REMAP_L2_BASE_MT7916 … #define MT_HIF_REMAP_BASE_L2_MT7916 … #define MT_INFRA_BASE … #define MT_WFSYS0_PHY_START … #define MT_WFSYS1_PHY_START … #define MT_WFSYS1_PHY_END … #define MT_CBTOP1_PHY_START … #define MT_CBTOP1_PHY_END … #define MT_CBTOP2_PHY_START … #define MT_INFRA_MCU_START … #define MT_INFRA_MCU_END … #define MT_CONN_INFRA_OFFSET(p) … /* CONN INFRA CFG */ #define MT_CONN_INFRA_BASE … #define MT_CONN_INFRA(ofs) … #define MT_CONN_INFRA_EFUSE … #define MT_CONN_INFRA_ADIE_RESET … #define MT_CONN_INFRA_ADIE1_RESET_MASK … #define MT_CONN_INFRA_ADIE2_RESET_MASK … #define MT_CONN_INFRA_OSC_RC_EN … #define MT_CONN_INFRA_OSC_CTRL … #define MT_CONN_INFRA_OSC_RC_EN_MASK … #define MT_CONN_INFRA_OSC_STB_TIME_MASK … #define MT_CONN_INFRA_HW_CTRL … #define MT_CONN_INFRA_HW_CTRL_MASK … #define MT_CONN_INFRA_WF_SLP_PROT … #define MT_CONN_INFRA_WF_SLP_PROT_MASK … #define MT_CONN_INFRA_WF_SLP_PROT_RDY … #define MT_CONN_INFRA_CONN_WF_MASK … #define MT_CONN_INFRA_CONN … #define MT_CONN_INFRA_EMI_REQ … #define MT_CONN_INFRA_EMI_REQ_MASK … #define MT_CONN_INFRA_INFRA_REQ_MASK … /* AFE */ #define MT_AFE_CTRL_BASE(_band) … #define MT_AFE_CTRL(_band, ofs) … #define MT_AFE_DIG_EN_01(_band) … #define MT_AFE_DIG_EN_02(_band) … #define MT_AFE_DIG_EN_03(_band) … #define MT_AFE_DIG_TOP_01(_band) … #define MT_AFE_PLL_STB_TIME(_band) … #define MT_AFE_PLL_STB_TIME_MASK … #define MT_AFE_PLL_STB_TIME_VAL … #define MT_AFE_BPLL_CFG_MASK … #define MT_AFE_WPLL_CFG_MASK … #define MT_AFE_MCU_WPLL_CFG_MASK … #define MT_AFE_MCU_BPLL_CFG_MASK … #define MT_AFE_PLL_CFG_MASK … #define MT_AFE_PLL_CFG_VAL … #define MT_AFE_DIG_TOP_01_MASK … #define MT_AFE_DIG_TOP_01_VAL … #define MT_AFE_RG_WBG_EN_RCK_MASK … #define MT_AFE_RG_WBG_EN_BPLL_UP_MASK … #define MT_AFE_RG_WBG_EN_WPLL_UP_MASK … #define MT_AFE_RG_WBG_EN_PLL_UP_MASK … #define MT_AFE_RG_WBG_EN_TXCAL_WF4 … #define MT_AFE_RG_WBG_EN_TXCAL_BT … #define MT_AFE_RG_WBG_EN_TXCAL_WF3 … #define MT_AFE_RG_WBG_EN_TXCAL_WF2 … #define MT_AFE_RG_WBG_EN_TXCAL_WF1 … #define MT_AFE_RG_WBG_EN_TXCAL_WF0 … #define MT_ADIE_SLP_CTRL_BASE(_band) … #define MT_ADIE_SLP_CTRL(_band, ofs) … #define MT_ADIE_SLP_CTRL_CK0(_band) … /* ADIE */ #define MT_ADIE_CHIP_ID … #define MT_ADIE_VERSION_MASK … #define MT_ADIE_CHIP_ID_MASK … #define MT_ADIE_IDX0 … #define MT_ADIE_IDX1 … #define MT_ADIE_RG_TOP_THADC_BG … #define MT_ADIE_VRPI_SEL_CR_MASK … #define MT_ADIE_VRPI_SEL_EFUSE_MASK … #define MT_ADIE_RG_TOP_THADC … #define MT_ADIE_PGA_GAIN_MASK … #define MT_ADIE_PGA_GAIN_EFUSE_MASK … #define MT_ADIE_LDO_CTRL_MASK … #define MT_ADIE_LDO_CTRL_EFUSE_MASK … #define MT_AFE_RG_ENCAL_WBTAC_IF_SW … #define MT_ADIE_EFUSE_RDATA0 … #define MT_ADIE_EFUSE2_CTRL … #define MT_ADIE_EFUSE_CTRL_MASK … #define MT_ADIE_EFUSE_CFG … #define MT_ADIE_EFUSE_MODE_MASK … #define MT_ADIE_EFUSE_ADDR_MASK … #define MT_ADIE_EFUSE_VALID_MASK … #define MT_ADIE_EFUSE_KICK_MASK … #define MT_ADIE_THADC_ANALOG … #define MT_ADIE_THADC_SLOP … #define MT_ADIE_ANA_EN_MASK … #define MT_ADIE_7975_XTAL_CAL … #define MT_ADIE_TRIM_MASK … #define MT_ADIE_EFUSE_TRIM_MASK … #define MT_ADIE_XO_TRIM_EN_MASK … #define MT_ADIE_XTAL_DECREASE_MASK … #define MT_ADIE_7975_XO_TRIM2 … #define MT_ADIE_7975_XO_TRIM3 … #define MT_ADIE_7975_XO_TRIM4 … #define MT_ADIE_7975_XTAL_EN … #define MT_ADIE_XO_TRIM_FLOW … #define MT_ADIE_XTAL_AXM_80M_OSC … #define MT_ADIE_XTAL_AXM_40M_OSC … #define MT_ADIE_XTAL_TRIM1_80M_OSC … #define MT_ADIE_XTAL_TRIM1_40M_OSC … #define MT_ADIE_WRI_CK_SEL … #define MT_ADIE_RG_STRAP_PIN_IN … #define MT_ADIE_XTAL_C1 … #define MT_ADIE_XTAL_C2 … #define MT_ADIE_RG_XO_01 … #define MT_ADIE_RG_XO_03 … #define MT_ADIE_CLK_EN … #define MT_ADIE_7975_XTAL … #define MT_ADIE_7975_XTAL_EN_MASK … #define MT_ADIE_7975_COCLK … #define MT_ADIE_7975_XO_2 … #define MT_ADIE_7975_XO_2_FIX_EN … #define MT_ADIE_7975_XO_CTRL2 … #define MT_ADIE_7975_XO_CTRL2_C1_MASK … #define MT_ADIE_7975_XO_CTRL2_C2_MASK … #define MT_ADIE_7975_XO_CTRL2_MASK … #define MT_ADIE_7975_XO_CTRL6 … #define MT_ADIE_7975_XO_CTRL6_MASK … /* TOP SPI */ #define MT_TOP_SPI_ADIE_BASE(_band) … #define MT_TOP_SPI_ADIE(_band, ofs) … #define MT_TOP_SPI_BUSY_CR(_band) … #define MT_TOP_SPI_POLLING_BIT … #define MT_TOP_SPI_ADDR_CR(_band) … #define MT_TOP_SPI_READ_ADDR_FORMAT … #define MT_TOP_SPI_WRITE_ADDR_FORMAT … #define MT_TOP_SPI_WRITE_DATA_CR(_band) … #define MT_TOP_SPI_READ_DATA_CR(_band) … /* CONN INFRA CKGEN */ #define MT_INFRA_CKGEN_BASE … #define MT_INFRA_CKGEN(ofs) … #define MT_INFRA_CKGEN_BUS … #define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK … #define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK … #define MT_INFRA_CKGEN_BUS_WPLL_DIV_1 … #define MT_INFRA_CKGEN_BUS_WPLL_DIV_2 … #define MT_INFRA_CKGEN_RFSPI_WPLL_DIV … #define MT_INFRA_CKGEN_DIV_SEL_MASK … #define MT_INFRA_CKGEN_DIV_EN_MASK … /* CONN INFRA BUS */ #define MT_INFRA_BUS_BASE … #define MT_INFRA_BUS(ofs) … #define MT_INFRA_BUS_OFF_TIMEOUT … #define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK … #define MT_INFRA_BUS_TIMEOUT_EN_MASK … #define MT_INFRA_BUS_ON_TIMEOUT … #define MT_INFRA_BUS_EMI_START … #define MT_INFRA_BUS_EMI_END … /* CONN_INFRA_SKU */ #define MT_CONNINFRA_SKU_DEC_ADDR … #define MT_CONNINFRA_SKU_MASK … #define MT_ADIE_TYPE_MASK … /* FW MODE SYNC */ #define MT_FW_ASSERT_STAT … #define MT_FW_EXCEPT_TYPE … #define MT_FW_EXCEPT_COUNT … #define MT_FW_CIRQ_COUNT … #define MT_FW_CIRQ_IDX … #define MT_FW_CIRQ_LISR … #define MT_FW_TASK_ID … #define MT_FW_TASK_IDX … #define MT_FW_TASK_QID1 … #define MT_FW_TASK_QID2 … #define MT_FW_TASK_START … #define MT_FW_TASK_END … #define MT_FW_TASK_SIZE … #define MT_FW_LAST_MSG_ID … #define MT_FW_EINT_INFO … #define MT_FW_SCHED_INFO … #define MT_SWDEF_BASE … #define MT_SWDEF(ofs) … #define MT_SWDEF_MODE … #define MT_SWDEF_NORMAL_MODE … #define MT_SWDEF_ICAP_MODE … #define MT_SWDEF_SPECTRUM_MODE … #define MT_SWDEF_SER_STATS … #define MT_SWDEF_PLE_STATS … #define MT_SWDEF_PLE1_STATS … #define MT_SWDEF_PLE_AMSDU_STATS … #define MT_SWDEF_PSE_STATS … #define MT_SWDEF_PSE1_STATS … #define MT_SWDEF_LAMC_WISR6_BN0_STATS … #define MT_SWDEF_LAMC_WISR6_BN1_STATS … #define MT_SWDEF_LAMC_WISR7_BN0_STATS … #define MT_SWDEF_LAMC_WISR7_BN1_STATS … #define MT_DIC_CMD_REG_BASE … #define MT_DIC_CMD_REG(ofs) … #define MT_DIC_CMD_REG_CMD … #define MT_CPU_UTIL_BASE … #define MT_CPU_UTIL(ofs) … #define MT_CPU_UTIL_BUSY_PCT … #define MT_CPU_UTIL_PEAK_BUSY_PCT … #define MT_CPU_UTIL_IDLE_CNT … #define MT_CPU_UTIL_PEAK_IDLE_CNT … #define MT_CPU_UTIL_CTRL … /* LED */ #define MT_LED_TOP_BASE … #define MT_LED_PHYS(_n) … #define MT_LED_CTRL(_n) … #define MT_LED_CTRL_KICK … #define MT_LED_CTRL_BAND … #define MT_LED_CTRL_BLINK_MODE … #define MT_LED_CTRL_POLARITY … #define MT_LED_TX_BLINK(_n) … #define MT_LED_TX_BLINK_ON_MASK … #define MT_LED_TX_BLINK_OFF_MASK … #define MT_LED_STATUS_0(_n) … #define MT_LED_STATUS_1(_n) … #define MT_LED_STATUS_OFF … #define MT_LED_STATUS_ON … #define MT_LED_STATUS_DURATION … #define MT_LED_EN(_n) … #define MT_LED_GPIO_MUX0 … #define MT_LED_GPIO_MUX1 … #define MT_LED_GPIO_MUX2 … #define MT_LED_GPIO_MUX3 … /* MT TOP */ #define MT_TOP_BASE … #define MT_TOP(ofs) … #define MT_TOP_LPCR_HOST_BAND(_band) … #define MT_TOP_LPCR_HOST_FW_OWN … #define MT_TOP_LPCR_HOST_DRV_OWN … #define MT_TOP_LPCR_HOST_FW_OWN_STAT … #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) … #define MT_TOP_LPCR_HOST_BAND_STAT … #define MT_TOP_MISC … #define MT_TOP_MISC_FW_STATE … #define MT_TOP_WFSYS_WAKEUP … #define MT_TOP_WFSYS_WAKEUP_MASK … #define MT_TOP_MCU_EMI_BASE … #define MT_TOP_MCU_EMI_BASE_MASK … #define MT_TOP_WF_AP_PERI_BASE … #define MT_TOP_WF_AP_PERI_BASE_MASK … #define MT_TOP_EFUSE_BASE … #define MT_TOP_EFUSE_BASE_MASK … #define MT_TOP_CONN_INFRA_WAKEUP … #define MT_TOP_CONN_INFRA_WAKEUP_MASK … #define MT_TOP_WFSYS_RESET_STATUS … #define MT_TOP_WFSYS_RESET_STATUS_MASK … /* SEMA */ #define MT_SEMA_BASE … #define MT_SEMA(ofs) … #define MT_SEMA_RFSPI_STATUS … #define MT_SEMA_RFSPI_RELEASE … #define MT_SEMA_RFSPI_STATUS_MASK … /* MCU BUS */ #define MT_MCU_BUS_BASE … #define MT_MCU_BUS(ofs) … #define MT_MCU_BUS_TIMEOUT … #define MT_MCU_BUS_TIMEOUT_SET_MASK … #define MT_MCU_BUS_TIMEOUT_CG_EN_MASK … #define MT_MCU_BUS_TIMEOUT_EN_MASK … #define MT_MCU_BUS_REMAP … /* TOP CFG */ #define MT_TOP_CFG_BASE … #define MT_TOP_CFG(ofs) … #define MT_TOP_CFG_IP_VERSION_ADDR … /* TOP CFG ON */ #define MT_TOP_CFG_ON_BASE … #define MT_TOP_CFG_ON(ofs) … #define MT_TOP_CFG_ON_ROM_IDX … /* SLP CTRL */ #define MT_SLP_BASE … #define MT_SLP(ofs) … #define MT_SLP_STATUS … #define MT_SLP_WFDMA2CONN_MASK … #define MT_SLP_CTRL_EN_MASK … #define MT_SLP_CTRL_BSY_MASK … /* MCU BUS DBG */ #define MT_MCU_BUS_DBG_BASE … #define MT_MCU_BUS_DBG(ofs) … #define MT_MCU_BUS_DBG_TIMEOUT … #define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK … #define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK … #define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK … #define MT_HW_BOUND … #define MT_HW_REV … #define MT_WF_SUBSYS_RST … /* PCIE MAC */ #define MT_PCIE_MAC_BASE … #define MT_PCIE_MAC(ofs) … #define MT_PCIE_MAC_INT_ENABLE … #define MT_PCIE1_MAC_INT_ENABLE … #define MT_PCIE1_MAC_INT_ENABLE_MT7916 … #define MT_WM_MCU_PC … #define MT_WA_MCU_PC … /* PP TOP */ #define MT_WF_PP_TOP_BASE … #define MT_WF_PP_TOP(ofs) … #define MT_WF_PP_TOP_RXQ_WFDMA_CF_5 … #define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK … #define MT_WF_IRPI_BASE … #define MT_WF_IRPI(ofs) … #define MT_WF_IRPI_NSS(phy, nss) … #define MT_WF_IRPI_NSS_MT7916(phy, nss) … /* PHY */ #define MT_WF_PHY_BASE … #define MT_WF_PHY(ofs) … #define MT_WF_PHY_RX_CTRL1(_phy) … #define MT_WF_PHY_RX_CTRL1_MT7916(_phy) … #define MT_WF_PHY_RX_CTRL1_IPI_EN … #define MT_WF_PHY_RX_CTRL1_STSCNT_EN … #define MT_WF_PHY_RXTD12(_phy) … #define MT_WF_PHY_RXTD12_MT7916(_phy) … #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY … #define MT_WF_PHY_RXTD12_IRPI_SW_CLR … #define MT_WF_PHY_TPC_CTRL_STAT(_phy) … #define MT_WF_PHY_TPC_CTRL_STAT_MT7916(_phy) … #define MT_WF_PHY_TPC_POWER … #define MT_MCU_WM_CIRQ_BASE … #define MT_MCU_WM_CIRQ(ofs) … #define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR … #define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR … #define MT_MCU_WM_CIRQ_EINT_MASK_CLR_ADDR … #define MT_MCU_WM_CIRQ_EINT_SOFT_ADDR … #endif
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