/* SPDX-License-Identifier: ISC */ /* * Copyright (C) 2022 MediaTek Inc. */ #ifndef __MT7996_REGS_H #define __MT7996_REGS_H struct __map { … }; struct __base { … }; /* used to differentiate between generations */ struct mt7996_reg_desc { … }; enum base_rev { … }; #define __BASE(_id, _band) … enum offs_rev { … }; #define __OFFS(id) … /* RRO TOP */ #define MT_RRO_TOP_BASE … #define MT_RRO_TOP(ofs) … #define MT_RRO_BA_BITMAP_BASE0 … #define MT_RRO_BA_BITMAP_BASE1 … #define WF_RRO_AXI_MST_CFG … #define WF_RRO_AXI_MST_CFG_DIDX_OK … #define MT_RRO_ADDR_ARRAY_BASE1 … #define MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE … #define MT_RRO_IND_CMD_SIGNATURE_BASE0 … #define MT_RRO_IND_CMD_SIGNATURE_BASE1 … #define MT_RRO_IND_CMD_0_CTRL0 … #define MT_RRO_IND_CMD_SIGNATURE_BASE1_EN … #define MT_RRO_PARTICULAR_CFG0 … #define MT_RRO_PARTICULAR_CFG1 … #define MT_RRO_PARTICULAR_CONFG_EN … #define MT_RRO_PARTICULAR_SID … #define MT_RRO_BA_BITMAP_BASE_EXT0 … #define MT_RRO_BA_BITMAP_BASE_EXT1 … #define MT_RRO_HOST_INT_ENA … #define MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA … #define MT_RRO_ADDR_ELEM_SEG_ADDR0 … #define MT_RRO_ACK_SN_CTRL … #define MT_RRO_ACK_SN_CTRL_SN_MASK … #define MT_RRO_ACK_SN_CTRL_SESSION_MASK … #define MT_RRO_DBG_RD_CTRL … #define MT_RRO_DBG_RD_ADDR … #define MT_RRO_DBG_RD_EXEC … #define MT_RRO_DBG_RDAT_DW(_n) … #define MT_MCU_INT_EVENT … #define MT_MCU_INT_EVENT_DMA_STOPPED … #define MT_MCU_INT_EVENT_DMA_INIT … #define MT_MCU_INT_EVENT_RESET_DONE … /* PLE */ #define MT_PLE_BASE … #define MT_PLE(ofs) … #define MT_FL_Q_EMPTY … #define MT_FL_Q0_CTRL … #define MT_FL_Q2_CTRL … #define MT_FL_Q3_CTRL … #define MT_PLE_FREEPG_CNT … #define MT_PLE_FREEPG_HEAD_TAIL … #define MT_PLE_PG_HIF_GROUP … #define MT_PLE_HIF_PG_INFO … #define MT_PLE_AC_QEMPTY(ac, n) … #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) … /* WF MDP TOP */ #define MT_MDP_BASE … #define MT_MDP(ofs) … #define MT_MDP_DCR2 … #define MT_MDP_DCR2_RX_TRANS_SHORT … /* TMAC: band 0(0x820e4000), band 1(0x820f4000), band 2(0x830e4000) */ #define MT_WF_TMAC_BASE(_band) … #define MT_WF_TMAC(_band, ofs) … #define MT_TMAC_TCR0(_band) … #define MT_TMAC_TCR0_TX_BLINK … #define MT_TMAC_CDTR(_band) … #define MT_TMAC_ODTR(_band) … #define MT_TIMEOUT_VAL_PLCP … #define MT_TIMEOUT_VAL_CCA … #define MT_TMAC_ICR0(_band) … #define MT_IFS_EIFS_OFDM … #define MT_IFS_RIFS … #define MT_IFS_SIFS … #define MT_IFS_SLOT … #define MT_TMAC_ICR1(_band) … #define MT_IFS_EIFS_CCK … /* WF DMA TOP: band 0(0x820e7000), band 1(0x820f7000), band 2(0x830e7000) */ #define MT_WF_DMA_BASE(_band) … #define MT_WF_DMA(_band, ofs) … #define MT_DMA_DCR0(_band) … #define MT_DMA_DCR0_RXD_G5_EN … #define MT_DMA_TCRF1(_band) … #define MT_DMA_TCRF1_QIDX … /* WTBLOFF TOP: band 0(0x820e9000), band 1(0x820f9000), band 2(0x830e9000) */ #define MT_WTBLOFF_BASE(_band) … #define MT_WTBLOFF(_band, ofs) … #define MT_WTBLOFF_RSCR(_band) … #define MT_WTBLOFF_RSCR_RCPI_MODE … #define MT_WTBLOFF_RSCR_RCPI_PARAM … /* ETBF: band 0(0x820ea000), band 1(0x820fa000), band 2(0x830ea000) */ #define MT_WF_ETBF_BASE(_band) … #define MT_WF_ETBF(_band, ofs) … #define MT_ETBF_RX_FB_CONT(_band) … #define MT_ETBF_RX_FB_BW … #define MT_ETBF_RX_FB_NC … #define MT_ETBF_RX_FB_NR … /* LPON: band 0(0x820eb000), band 1(0x820fb000), band 2(0x830eb000) */ #define MT_WF_LPON_BASE(_band) … #define MT_WF_LPON(_band, ofs) … #define MT_LPON_UTTR0(_band) … #define MT_LPON_UTTR1(_band) … #define MT_LPON_FRCR(_band) … #define MT_LPON_TCR(_band, n) … #define MT_LPON_TCR_SW_MODE … #define MT_LPON_TCR_SW_WRITE … #define MT_LPON_TCR_SW_ADJUST … #define MT_LPON_TCR_SW_READ … /* MIB: band 0(0x820ed000), band 1(0x820fd000), band 2(0x830ed000)*/ /* These counters are (mostly?) clear-on-read. So, some should not * be read at all in case firmware is already reading them. These * are commented with 'DNR' below. The DNR stats will be read by querying * the firmware API for the appropriate message. For counters the driver * does read, the driver should accumulate the counters. */ #define MT_WF_MIB_BASE(_band) … #define MT_WF_MIB(_band, ofs) … #define MT_MIB_BSCR0(_band) … #define MT_MIB_BSCR1(_band) … #define MT_MIB_BSCR2(_band) … #define MT_MIB_BSCR3(_band) … #define MT_MIB_BSCR4(_band) … #define MT_MIB_BSCR5(_band) … #define MT_MIB_BSCR6(_band) … #define MT_MIB_BSCR7(_band) … #define MT_MIB_BSCR17(_band) … #define MT_MIB_TSCR5(_band) … #define MT_MIB_TSCR6(_band) … #define MT_MIB_TSCR7(_band) … #define MT_MIB_RSCR1(_band) … /* rx mpdu counter, full 32 bits */ #define MT_MIB_RSCR31(_band) … #define MT_MIB_RSCR33(_band) … #define MT_MIB_SDR6(_band) … #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK … #define MT_MIB_RVSR0(_band) … #define MT_MIB_RSCR35(_band) … #define MT_MIB_RSCR36(_band) … /* tx ampdu cnt, full 32 bits */ #define MT_MIB_TSCR0(_band) … #define MT_MIB_TSCR2(_band) … /* counts all mpdus in ampdu, regardless of success */ #define MT_MIB_TSCR3(_band) … /* counts all successfully tx'd mpdus in ampdu */ #define MT_MIB_TSCR4(_band) … /* rx ampdu count, 32-bit */ #define MT_MIB_RSCR27(_band) … /* rx ampdu bytes count, 32-bit */ #define MT_MIB_RSCR28(_band) … /* rx ampdu valid subframe count */ #define MT_MIB_RSCR29(_band) … /* rx ampdu valid subframe bytes count, 32bits */ #define MT_MIB_RSCR30(_band) … /* remaining windows protected stats */ #define MT_MIB_SDR27(_band) … #define MT_MIB_SDR27_TX_RWP_FAIL_CNT … #define MT_MIB_SDR28(_band) … #define MT_MIB_SDR28_TX_RWP_NEED_CNT … #define MT_MIB_RVSR1(_band) … /* rx blockack count, 32 bits */ #define MT_MIB_TSCR1(_band) … #define MT_MIB_BTSCR0(_band) … #define MT_MIB_BTSCR5(_band) … #define MT_MIB_BTSCR6(_band) … #define MT_MIB_BFTFCR(_band) … #define MT_TX_AGG_CNT(_band, n) … #define MT_MIB_ARNG(_band, n) … #define MT_MIB_ARNCR_RANGE(val, n) … /* UMIB */ #define MT_WF_UMIB_BASE … #define MT_WF_UMIB(ofs) … #define MT_UMIB_RPDCR(_band) … /* WTBLON TOP */ #define MT_WTBLON_TOP_BASE … #define MT_WTBLON_TOP(ofs) … #define MT_WTBLON_TOP_WDUCR … #define MT_WTBLON_TOP_WDUCR_GROUP … #define MT_WTBL_UPDATE … #define MT_WTBL_UPDATE_WLAN_IDX … #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR … #define MT_WTBL_UPDATE_BUSY … #define MT_WTBL_ITCR … #define MT_WTBL_ITCR_WR … #define MT_WTBL_ITCR_EXEC … #define MT_WTBL_ITDR0 … #define MT_WTBL_ITDR1 … #define MT_WTBL_SPE_IDX_SEL … /* WTBL */ #define MT_WTBL_BASE … #define MT_WTBL_LMAC_ID … #define MT_WTBL_LMAC_DW … #define MT_WTBL_LMAC_OFFS(_id, _dw) … /* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */ #define MT_WF_AGG_BASE(_band) … #define MT_WF_AGG(_band, ofs) … #define MT_AGG_ACR4(_band) … #define MT_AGG_ACR_PPDU_TXS2H … /* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */ #define MT_WF_ARB_BASE(_band) … #define MT_WF_ARB(_band, ofs) … #define MT_ARB_SCR(_band) … #define MT_ARB_SCR_TX_DISABLE … #define MT_ARB_SCR_RX_DISABLE … /* RMAC: band 0(0x820e5000), band 1(0x820f5000), band 2(0x830e5000), */ #define MT_WF_RMAC_BASE(_band) … #define MT_WF_RMAC(_band, ofs) … #define MT_WF_RFCR(_band) … #define MT_WF_RFCR_DROP_STBC_MULTI … #define MT_WF_RFCR_DROP_FCSFAIL … #define MT_WF_RFCR_DROP_PROBEREQ … #define MT_WF_RFCR_DROP_MCAST … #define MT_WF_RFCR_DROP_BCAST … #define MT_WF_RFCR_DROP_MCAST_FILTERED … #define MT_WF_RFCR_DROP_A3_MAC … #define MT_WF_RFCR_DROP_A3_BSSID … #define MT_WF_RFCR_DROP_A2_BSSID … #define MT_WF_RFCR_DROP_OTHER_BEACON … #define MT_WF_RFCR_DROP_FRAME_REPORT … #define MT_WF_RFCR_DROP_CTL_RSV … #define MT_WF_RFCR_DROP_CTS … #define MT_WF_RFCR_DROP_RTS … #define MT_WF_RFCR_DROP_DUPLICATE … #define MT_WF_RFCR_DROP_OTHER_BSS … #define MT_WF_RFCR_DROP_OTHER_UC … #define MT_WF_RFCR_DROP_OTHER_TIM … #define MT_WF_RFCR_DROP_NDPA … #define MT_WF_RFCR_DROP_UNWANTED_CTL … #define MT_WF_RFCR1(_band) … #define MT_WF_RFCR1_DROP_ACK … #define MT_WF_RFCR1_DROP_BF_POLL … #define MT_WF_RFCR1_DROP_BA … #define MT_WF_RFCR1_DROP_CFEND … #define MT_WF_RFCR1_DROP_CFACK … #define MT_WF_RMAC_MIB_AIRTIME0(_band) … #define MT_WF_RMAC_MIB_RXTIME_CLR … #define MT_WF_RMAC_MIB_ED_OFFSET … #define MT_WF_RMAC_MIB_OBSS_BACKOFF … #define MT_WF_RMAC_MIB_AIRTIME1(_band) … #define MT_WF_RMAC_MIB_NONQOSD_BACKOFF … #define MT_WF_RMAC_MIB_AIRTIME3(_band) … #define MT_WF_RMAC_MIB_QOS01_BACKOFF … #define MT_WF_RMAC_MIB_AIRTIME4(_band) … #define MT_WF_RMAC_MIB_QOS23_BACKOFF … #define MT_WF_RMAC_RSVD0(_band) … #define MT_WF_RMAC_RSVD0_EIFS_CLR … /* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */ #define MT_WF_RATE_BASE(_band) … #define MT_WF_RATE(_band, ofs) … #define MT_RATE_HRCR0(_band) … #define MT_RATE_HRCR0_CFEND_RATE … /* WFDMA0 */ #define MT_WFDMA0_BASE … #define MT_WFDMA0(ofs) … #define MT_WFDMA0_RST … #define MT_WFDMA0_RST_LOGIC_RST … #define MT_WFDMA0_RST_DMASHDL_ALL_RST … #define MT_WFDMA0_BUSY_ENA … #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 … #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 … #define MT_WFDMA0_BUSY_ENA_RX_FIFO … #define MT_WFDMA0_RX_INT_PCIE_SEL … #define MT_WFDMA0_RX_INT_SEL_RING3 … #define MT_WFDMA0_RX_INT_SEL_RING6 … #define MT_WFDMA0_MCU_HOST_INT_ENA … #define MT_WFDMA0_GLO_CFG … #define MT_WFDMA0_GLO_CFG_TX_DMA_EN … #define MT_WFDMA0_GLO_CFG_RX_DMA_EN … #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 … #define MT_WFDMA0_GLO_CFG_EXT_EN … #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO … #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO … #define MT_WFDMA0_PAUSE_RX_Q_45_TH … #define MT_WFDMA0_PAUSE_RX_Q_67_TH … #define MT_WFDMA0_PAUSE_RX_Q_89_TH … #define MT_WFDMA0_PAUSE_RX_Q_RRO_TH … #define WF_WFDMA0_GLO_CFG_EXT0 … #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD … #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE … #define WF_WFDMA0_GLO_CFG_EXT1 … #define WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE … #define WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE … #define MT_WFDMA0_RST_DTX_PTR … #define MT_WFDMA0_PRI_DLY_INT_CFG0 … #define MT_WFDMA0_PRI_DLY_INT_CFG1 … #define MT_WFDMA0_PRI_DLY_INT_CFG2 … /* WFDMA1 */ #define MT_WFDMA1_BASE … /* WFDMA CSR */ #define MT_WFDMA_EXT_CSR_BASE … #define MT_WFDMA_EXT_CSR(ofs) … #define MT_WFDMA_HOST_CONFIG … #define MT_WFDMA_HOST_CONFIG_PDMA_BAND … #define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1 … #define MT_WFDMA_EXT_CSR_HIF_MISC … #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY … #define MT_WFDMA_AXI_R2A_CTRL … #define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK … #define MT_PCIE_RECOG_ID … #define MT_PCIE_RECOG_ID_MASK … #define MT_PCIE_RECOG_ID_SEM … /* WFDMA0 PCIE1 */ #define MT_WFDMA0_PCIE1_BASE … #define MT_WFDMA0_PCIE1(ofs) … #define MT_INT_PCIE1_SOURCE_CSR_EXT … #define MT_INT_PCIE1_MASK_CSR … #define MT_WFDMA0_PCIE1_BUSY_ENA … #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 … #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 … #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO … /* WFDMA COMMON */ #define __RXQ(q) … #define __TXQ(q) … #define MT_Q_ID(q) … #define MT_Q_BASE(q) … #define MT_MCUQ_ID(q) … #define MT_TXQ_ID(q) … #define MT_RXQ_ID(q) … #define MT_MCUQ_RING_BASE(q) … #define MT_TXQ_RING_BASE(q) … #define MT_RXQ_RING_BASE(q) … #define MT_RXQ_RRO_IND_RING_BASE … #define MT_MCUQ_EXT_CTRL(q) … #define MT_RXQ_BAND1_CTRL(q) … #define MT_TXQ_EXT_CTRL(q) … #define MT_INT_SOURCE_CSR … #define MT_INT_MASK_CSR … #define MT_INT1_SOURCE_CSR … #define MT_INT1_MASK_CSR … #define MT_INT_RX_DONE_BAND0 … #define MT_INT_RX_DONE_BAND1 … #define MT_INT_RX_DONE_BAND2 … #define MT_INT_RX_DONE_WM … #define MT_INT_RX_DONE_WA … #define MT_INT_RX_DONE_WA_MAIN … #define MT_INT_RX_DONE_WA_EXT … #define MT_INT_RX_DONE_WA_TRI … #define MT_INT_RX_TXFREE_MAIN … #define MT_INT_RX_TXFREE_TRI … #define MT_INT_RX_DONE_BAND2_EXT … #define MT_INT_RX_TXFREE_EXT … #define MT_INT_MCU_CMD … #define MT_INT_RX_DONE_RRO_BAND0 … #define MT_INT_RX_DONE_RRO_BAND1 … #define MT_INT_RX_DONE_RRO_BAND2 … #define MT_INT_RX_DONE_RRO_IND … #define MT_INT_RX_DONE_MSDU_PG_BAND0 … #define MT_INT_RX_DONE_MSDU_PG_BAND1 … #define MT_INT_RX_DONE_MSDU_PG_BAND2 … #define MT_INT_RX(q) … #define MT_INT_TX_MCU(q) … #define MT_INT_RX_DONE_MCU … #define MT_INT_BAND0_RX_DONE … #define MT_INT_BAND1_RX_DONE … #define MT_INT_BAND2_RX_DONE … #define MT_INT_RRO_RX_DONE … #define MT_INT_RX_DONE_ALL … #define MT_INT_TX_DONE_FWDL … #define MT_INT_TX_DONE_MCU_WM … #define MT_INT_TX_DONE_MCU_WA … #define MT_INT_TX_DONE_BAND0 … #define MT_INT_TX_DONE_BAND1 … #define MT_INT_TX_DONE_BAND2 … #define MT_INT_TX_RX_DONE_EXT … #define MT_INT_TX_DONE_MCU … #define MT_MCU_CMD … #define MT_MCU_CMD_STOP_DMA … #define MT_MCU_CMD_RESET_DONE … #define MT_MCU_CMD_RECOVERY_DONE … #define MT_MCU_CMD_NORMAL_STATE … #define MT_MCU_CMD_ERROR_MASK … #define MT_MCU_CMD_WA_WDT … #define MT_MCU_CMD_WM_WDT … #define MT_MCU_CMD_WDT_MASK … /* l1/l2 remap */ #define MT_HIF_REMAP_L1 … #define MT_HIF_REMAP_L1_MASK … #define MT_HIF_REMAP_L1_OFFSET … #define MT_HIF_REMAP_L1_BASE … #define MT_HIF_REMAP_BASE_L1 … #define MT_HIF_REMAP_L2 … #define MT_HIF_REMAP_L2_MASK … #define MT_HIF_REMAP_L2_OFFSET … #define MT_HIF_REMAP_L2_BASE … #define MT_HIF_REMAP_BASE_L2 … #define MT_INFRA_BASE … #define MT_WFSYS0_PHY_START … #define MT_WFSYS1_PHY_START … #define MT_WFSYS1_PHY_END … #define MT_CBTOP1_PHY_START … #define MT_CBTOP1_PHY_END … #define MT_CBTOP2_PHY_START … #define MT_INFRA_MCU_START … #define MT_INFRA_MCU_END … /* FW MODE SYNC */ #define MT_FW_ASSERT_CNT … #define MT_FW_DUMP_STATE … #define MT_SWDEF_BASE … #define MT_SWDEF(ofs) … #define MT_SWDEF_MODE … #define MT_SWDEF_NORMAL_MODE … #define MT_SWDEF_SER_STATS … #define MT_SWDEF_PLE_STATS … #define MT_SWDEF_PLE1_STATS … #define MT_SWDEF_PLE_AMSDU_STATS … #define MT_SWDEF_PSE_STATS … #define MT_SWDEF_PSE1_STATS … #define MT_SWDEF_LAMC_WISR6_BN0_STATS … #define MT_SWDEF_LAMC_WISR6_BN1_STATS … #define MT_SWDEF_LAMC_WISR6_BN2_STATS … #define MT_SWDEF_LAMC_WISR7_BN0_STATS … #define MT_SWDEF_LAMC_WISR7_BN1_STATS … #define MT_SWDEF_LAMC_WISR7_BN2_STATS … /* LED */ #define MT_LED_TOP_BASE … #define MT_LED_PHYS(_n) … #define MT_LED_CTRL(_n) … #define MT_LED_CTRL_KICK … #define MT_LED_CTRL_BLINK_BAND_SEL … #define MT_LED_CTRL_BLINK_MODE … #define MT_LED_CTRL_POLARITY … #define MT_LED_TX_BLINK(_n) … #define MT_LED_TX_BLINK_ON_MASK … #define MT_LED_TX_BLINK_OFF_MASK … #define MT_LED_EN(_n) … /* CONN DBG */ #define MT_CONN_DBG_CTL_BASE … #define MT_CONN_DBG_CTL(ofs) … #define MT_CONN_DBG_CTL_OUT_SEL … #define MT_CONN_DBG_CTL_PC_LOG_SEL … #define MT_CONN_DBG_CTL_PC_LOG … #define MT_LED_GPIO_MUX2 … #define MT_LED_GPIO_MUX3 … #define MT_LED_GPIO_SEL_MASK … /* MT TOP */ #define MT_TOP_BASE … #define MT_TOP(ofs) … #define MT_TOP_LPCR_HOST_BAND(_band) … #define MT_TOP_LPCR_HOST_FW_OWN … #define MT_TOP_LPCR_HOST_DRV_OWN … #define MT_TOP_LPCR_HOST_FW_OWN_STAT … #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) … #define MT_TOP_LPCR_HOST_BAND_STAT … #define MT_TOP_MISC … #define MT_TOP_MISC_FW_STATE … #define MT_PAD_GPIO … #define MT_PAD_GPIO_ADIE_COMB … #define MT_HW_REV … #define MT_HW_REV1 … #define MT_WF_SUBSYS_RST … /* PCIE MAC */ #define MT_PCIE_MAC_BASE … #define MT_PCIE_MAC(ofs) … #define MT_PCIE_MAC_INT_ENABLE … #define MT_PCIE1_MAC_BASE … #define MT_PCIE1_MAC(ofs) … #define MT_PCIE1_MAC_INT_ENABLE … /* PHYRX CSD */ #define MT_WF_PHYRX_CSD_BASE … #define MT_WF_PHYRX_CSD(_band, _wf, ofs) … #define MT_WF_PHYRX_CSD_IRPI(_band, _wf) … /* PHYRX CTRL */ #define MT_WF_PHYRX_BAND_BASE … #define MT_WF_PHYRX_BAND(_band, ofs) … #define MT_WF_PHYRX_BAND_GID_TAB_VLD0(_band) … #define MT_WF_PHYRX_BAND_GID_TAB_VLD1(_band) … #define MT_WF_PHYRX_BAND_GID_TAB_POS0(_band) … #define MT_WF_PHYRX_BAND_GID_TAB_POS1(_band) … #define MT_WF_PHYRX_BAND_GID_TAB_POS2(_band) … #define MT_WF_PHYRX_BAND_GID_TAB_POS3(_band) … #define MT_WF_PHYRX_BAND_RX_CTRL1(_band) … #define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN … #define MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN … /* PHYRX CSD BAND */ #define MT_WF_PHYRX_CSD_BAND_RXTD12(_band) … #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY … #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR … /* CONN MCU EXCP CON */ #define MT_MCU_WM_EXCP_BASE … #define MT_MCU_WM_EXCP(ofs) … #define MT_MCU_WM_EXCP_PC_CTRL … #define MT_MCU_WM_EXCP_PC_LOG … #define MT_MCU_WM_EXCP_LR_CTRL … #define MT_MCU_WM_EXCP_LR_LOG … /* CONN AFE CTL CON */ #define MT_AFE_CTL_BASE … #define MT_AFE_CTL_BAND(_band, ofs) … #define MT_AFE_CTL_BAND_PLL_03(_band) … #define MT_AFE_CTL_BAND_PLL_03_MSB_EN … #endif
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