/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. * All rights reserved. */ #ifndef WILC_WLAN_H #define WILC_WLAN_H #include <linux/types.h> #include <linux/bitfield.h> /******************************************** * * Mac eth header length * ********************************************/ #define MAX_MAC_HDR_LEN … #define SUB_MSDU_HEADER_LENGTH … #define SNAP_HDR_LEN … #define ETHERNET_HDR_LEN … #define WORD_ALIGNMENT_PAD … #define ETH_ETHERNET_HDR_OFFSET … #define HOST_HDR_OFFSET … #define ETHERNET_HDR_LEN … #define IP_HDR_LEN … #define IP_HDR_OFFSET … #define UDP_HDR_OFFSET … #define UDP_HDR_LEN … #define UDP_DATA_OFFSET … #define ETH_CONFIG_PKT_HDR_LEN … #define ETH_CONFIG_PKT_HDR_OFFSET … /******************************************** * * Register Defines * ********************************************/ #define WILC_PERIPH_REG_BASE … #define WILC_CHANGING_VIR_IF … #define WILC_CHIPID … #define WILC_GLB_RESET_0 … #define WILC_PIN_MUX_0 … #define WILC_HOST_TX_CTRL … #define WILC_HOST_RX_CTRL_0 … #define WILC_HOST_RX_CTRL_1 … #define WILC_HOST_VMM_CTL … #define WILC_HOST_RX_CTRL … #define WILC_HOST_RX_EXTRA_SIZE … #define WILC_HOST_TX_CTRL_1 … #define WILC_INTR_REG_BASE … #define WILC_INTR_ENABLE … #define WILC_INTR2_ENABLE … #define WILC_INTR_POLARITY … #define WILC_INTR_TYPE … #define WILC_INTR_CLEAR … #define WILC_INTR_STATUS … #define WILC_RF_REVISION_ID … #define WILC_VMM_TBL_SIZE … #define WILC_VMM_TX_TBL_BASE … #define WILC_VMM_RX_TBL_BASE … #define WILC_VMM_BASE … #define WILC_VMM_CORE_CTL … #define WILC_VMM_TBL_CTL … #define WILC_VMM_TBL_ENTRY … #define WILC_VMM_TBL0_SIZE … #define WILC_VMM_TO_HOST_SIZE … #define WILC_VMM_CORE_CFG … #define WILC_VMM_TBL_ACTIVE … #define WILC_VMM_TBL_STATUS … #define WILC_SPI_REG_BASE … #define WILC_SPI_CTL … #define WILC_SPI_MASTER_DMA_ADDR … #define WILC_SPI_MASTER_DMA_COUNT … #define WILC_SPI_SLAVE_DMA_ADDR … #define WILC_SPI_SLAVE_DMA_COUNT … #define WILC_SPI_TX_MODE … #define WILC_SPI_PROTOCOL_CONFIG … #define WILC_SPI_INTR_CTL … #define WILC_SPI_INT_STATUS … #define WILC_SPI_INT_CLEAR … #define WILC_SPI_WAKEUP_REG … #define WILC_SPI_WAKEUP_BIT … #define WILC_SPI_CLK_STATUS_REG … #define WILC_SPI_CLK_STATUS_BIT … #define WILC_SPI_HOST_TO_FW_REG … #define WILC_SPI_HOST_TO_FW_BIT … #define WILC_SPI_FW_TO_HOST_REG … #define WILC_SPI_FW_TO_HOST_BIT … #define WILC_SPI_PROTOCOL_OFFSET … #define WILC_SPI_CLOCKLESS_ADDR_LIMIT … /* Functions IO enables bits */ #define WILC_SDIO_CCCR_IO_EN_FUNC1 … /* Function/Interrupt enables bits */ #define WILC_SDIO_CCCR_IEN_MASTER … #define WILC_SDIO_CCCR_IEN_FUNC1 … /* Abort CCCR register bits */ #define WILC_SDIO_CCCR_ABORT_RESET … /* Vendor specific CCCR registers */ #define WILC_SDIO_WAKEUP_REG … #define WILC_SDIO_WAKEUP_BIT … #define WILC_SDIO_CLK_STATUS_REG … #define WILC_SDIO_CLK_STATUS_BIT … #define WILC_SDIO_INTERRUPT_DATA_SZ_REG … #define WILC_SDIO_VMM_TBL_CTRL_REG … #define WILC_SDIO_IRQ_FLAG_REG … #define WILC_SDIO_IRQ_CLEAR_FLAG_REG … #define WILC_SDIO_HOST_TO_FW_REG … #define WILC_SDIO_HOST_TO_FW_BIT … #define WILC_SDIO_FW_TO_HOST_REG … #define WILC_SDIO_FW_TO_HOST_BIT … /* Function 1 specific FBR register */ #define WILC_SDIO_FBR_CSA_REG … #define WILC_SDIO_FBR_DATA_REG … #define WILC_SDIO_F1_DATA_REG … #define WILC_SDIO_EXT_IRQ_FLAG_REG … #define WILC_AHB_DATA_MEM_BASE … #define WILC_AHB_SHARE_MEM_BASE … #define WILC_VMM_TBL_RX_SHADOW_BASE … #define WILC_VMM_TBL_RX_SHADOW_SIZE … #define WILC_FW_HOST_COMM … #define WILC_GP_REG_0 … #define WILC_GP_REG_1 … #define GLOBAL_MODE_CONTROL … #define PWR_SEQ_MISC_CTRL … #define WILC_GLOBAL_MODE_ENABLE_WIFI … #define WILC_PWR_SEQ_ENABLE_WIFI_SLEEP … #define WILC_HAVE_SDIO_IRQ_GPIO … #define WILC_HAVE_USE_PMU … #define WILC_HAVE_SLEEP_CLK_SRC_RTC … #define WILC_HAVE_SLEEP_CLK_SRC_XO … #define WILC_HAVE_EXT_PA_INV_TX_RX … #define WILC_HAVE_LEGACY_RF_SETTINGS … #define WILC_HAVE_XTAL_24 … #define WILC_HAVE_DISABLE_WILC_UART … #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE … #define WILC_CORTUS_INTERRUPT_BASE … #define WILC_CORTUS_INTERRUPT_1 … #define WILC_CORTUS_INTERRUPT_2 … /* tx control register 1 to 4 for RX */ #define WILC_REG_4_TO_1_RX … /* tx control register 1 to 4 for TX Bank_0 */ #define WILC_REG_4_TO_1_TX_BANK0 … #define WILC_CORTUS_RESET_MUX_SEL … #define WILC_CORTUS_BOOT_REGISTER … #define WILC_CORTUS_BOOT_FROM_IRAM … #define WILC_1000_BASE_ID … #define WILC_1000_BASE_ID_2A … #define WILC_1000_BASE_ID_2A_REV1 … #define WILC_1000_BASE_ID_2B … #define WILC_1000_BASE_ID_2B_REV1 … #define WILC_1000_BASE_ID_2B_REV2 … #define WILC_CHIP_REV_FIELD … /******************************************** * * Wlan Defines * ********************************************/ #define WILC_CFG_PKT … #define WILC_NET_PKT … #define WILC_MGMT_PKT … #define WILC_CFG_SET … #define WILC_CFG_QUERY … #define WILC_CFG_RSP … #define WILC_CFG_RSP_STATUS … #define WILC_CFG_RSP_SCAN … #define WILC_ABORT_REQ_BIT … #define WILC_RX_BUFF_SIZE … #define WILC_TX_BUFF_SIZE … #define NQUEUES … #define AC_BUFFER_SIZE … #define VO_AC_COUNT_FIELD … #define VO_AC_ACM_STAT_FIELD … #define VI_AC_COUNT_FIELD … #define VI_AC_ACM_STAT_FIELD … #define BE_AC_COUNT_FIELD … #define BE_AC_ACM_STAT_FIELD … #define BK_AC_COUNT_FIELD … #define BK_AC_ACM_STAT_FIELD … #define WILC_PKT_HDR_CONFIG_FIELD … #define WILC_PKT_HDR_OFFSET_FIELD … #define WILC_PKT_HDR_TOTAL_LEN_FIELD … #define WILC_PKT_HDR_LEN_FIELD … #define WILC_INTERRUPT_DATA_SIZE … #define WILC_VMM_BUFFER_SIZE … #define WILC_VMM_HDR_TYPE … #define WILC_VMM_HDR_MGMT_FIELD … #define WILC_VMM_HDR_PKT_SIZE … #define WILC_VMM_HDR_BUFF_SIZE … #define WILC_VMM_ENTRY_COUNT … #define WILC_VMM_ENTRY_AVAILABLE … /*******************************************/ /* E0 and later Interrupt flags. */ /*******************************************/ /*******************************************/ /* E0 and later Interrupt flags. */ /* IRQ Status word */ /* 15:0 = DMA count in words. */ /* 16: INT0 flag */ /* 17: INT1 flag */ /* 18: INT2 flag */ /* 19: INT3 flag */ /* 20: INT4 flag */ /* 21: INT5 flag */ /*******************************************/ #define IRG_FLAGS_OFFSET … #define IRQ_DMA_WD_CNT_MASK … #define INT_0 … #define INT_1 … #define INT_2 … #define INT_3 … #define INT_4 … #define INT_5 … #define MAX_NUM_INT … #define IRG_FLAGS_MASK … /*******************************************/ /* E0 and later Interrupt flags. */ /* IRQ Clear word */ /* 0: Clear INT0 */ /* 1: Clear INT1 */ /* 2: Clear INT2 */ /* 3: Clear INT3 */ /* 4: Clear INT4 */ /* 5: Clear INT5 */ /* 6: Select VMM table 1 */ /* 7: Select VMM table 2 */ /* 8: Enable VMM */ /*******************************************/ #define CLR_INT0 … #define CLR_INT1 … #define CLR_INT2 … #define CLR_INT3 … #define CLR_INT4 … #define CLR_INT5 … #define SEL_VMM_TBL0 … #define SEL_VMM_TBL1 … #define EN_VMM … #define DATA_INT_EXT … #define ALL_INT_EXT … #define NUM_INT_EXT … #define UNHANDLED_IRQ_MASK … #define DATA_INT_CLR … #define ENABLE_RX_VMM … #define ENABLE_TX_VMM … /* time for expiring the completion of cfg packets */ #define WILC_CFG_PKTS_TIMEOUT … #define IS_MANAGMEMENT … #define IS_MANAGMEMENT_CALLBACK … #define IS_MGMT_STATUS_SUCCES … #define IS_MGMT_AUTH_PKT … #define WILC_WID_TYPE … #define WILC_VMM_ENTRY_FULL_RETRY … /******************************************** * * Tx/Rx Queue Structure * ********************************************/ enum ip_pkt_priority { … }; struct txq_entry_t { … }; struct txq_fw_recv_queue_stat { … }; struct txq_handle { … }; struct rxq_entry_t { … }; /******************************************** * * Host IF Structure * ********************************************/ struct wilc; struct wilc_hif_func { … }; #define WILC_MAX_CFG_FRAME_SIZE … struct tx_complete_data { … }; struct wilc_cfg_cmd_hdr { … }; struct wilc_cfg_frame { … }; struct wilc_cfg_rsp { … }; struct wilc_vif; static inline bool is_wilc1000(u32 id) { … } int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer, u32 buffer_size); int wilc_wlan_start(struct wilc *wilc); int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif); int wilc_wlan_txq_add_net_pkt(struct net_device *dev, struct tx_complete_data *tx_data, u8 *buffer, u32 buffer_size, void (*tx_complete_fn)(void *, int)); int wilc_wlan_handle_txq(struct wilc *wl, u32 *txq_count); void wilc_handle_isr(struct wilc *wilc); void wilc_wlan_cleanup(struct net_device *dev); int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer, u32 buffer_size, int commit, u32 drv_handler); int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit, u32 drv_handler); int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer, u32 buffer_size, void (*func)(void *, int)); void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value); int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc); netdev_tx_t wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev); void wilc_wfi_p2p_rx(struct wilc_vif *vif, u8 *buff, u32 size); bool wilc_wfi_mgmt_frame_rx(struct wilc_vif *vif, u8 *buff, u32 size); void host_wakeup_notify(struct wilc *wilc); void host_sleep_notify(struct wilc *wilc); void chip_allow_sleep(struct wilc *wilc); void chip_wakeup(struct wilc *wilc); int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids, u32 count); int wilc_wlan_init(struct net_device *dev); u32 wilc_get_chipid(struct wilc *wilc, bool update); int wilc_load_mac_from_nv(struct wilc *wilc); #endif
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