/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Copyright (C) 2009 - 2010 Ivo van Doorn <[email protected]> * Copyright (C) 2009 Alban Browaeys <[email protected]> * Copyright (C) 2009 Felix Fietkau <[email protected]> * Copyright (C) 2009 Luis Correia <[email protected]> * Copyright (C) 2009 Mattias Nissler <[email protected]> * Copyright (C) 2009 Mark Asselstine <[email protected]> * Copyright (C) 2009 Xose Vazquez Perez <[email protected]> * Copyright (C) 2009 Bart Zolnierkiewicz <[email protected]> * <http://rt2x00.serialmonkey.com> */ /* Module: rt2800mmio * Abstract: forward declarations for the rt2800mmio module. */ #ifndef RT2800MMIO_H #define RT2800MMIO_H /* * Queue register offset macros */ #define TX_QUEUE_REG_OFFSET … #define TX_BASE_PTR(__x) … #define TX_MAX_CNT(__x) … #define TX_CTX_IDX(__x) … #define TX_DTX_IDX(__x) … /* * DMA descriptor defines. */ #define TXD_DESC_SIZE … #define RXD_DESC_SIZE … /* * TX descriptor format for TX, PRIO and Beacon Ring. */ /* * Word0 */ #define TXD_W0_SD_PTR0 … /* * Word1 */ #define TXD_W1_SD_LEN1 … #define TXD_W1_LAST_SEC1 … #define TXD_W1_BURST … #define TXD_W1_SD_LEN0 … #define TXD_W1_LAST_SEC0 … #define TXD_W1_DMA_DONE … /* * Word2 */ #define TXD_W2_SD_PTR1 … /* * Word3 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler. * 0:MGMT, 1:HCCA 2:EDCA */ #define TXD_W3_WIV … #define TXD_W3_QSEL … #define TXD_W3_TCO … #define TXD_W3_UCO … #define TXD_W3_ICO … /* * RX descriptor format for RX Ring. */ /* * Word0 */ #define RXD_W0_SDP0 … /* * Word1 */ #define RXD_W1_SDL1 … #define RXD_W1_SDL0 … #define RXD_W1_LS0 … #define RXD_W1_DMA_DONE … /* * Word2 */ #define RXD_W2_SDP1 … /* * Word3 * AMSDU: RX with 802.3 header, not 802.11 header. * DECRYPTED: This frame is being decrypted. */ #define RXD_W3_BA … #define RXD_W3_DATA … #define RXD_W3_NULLDATA … #define RXD_W3_FRAG … #define RXD_W3_UNICAST_TO_ME … #define RXD_W3_MULTICAST … #define RXD_W3_BROADCAST … #define RXD_W3_MY_BSS … #define RXD_W3_CRC_ERROR … #define RXD_W3_CIPHER_ERROR … #define RXD_W3_AMSDU … #define RXD_W3_HTC … #define RXD_W3_RSSI … #define RXD_W3_L2PAD … #define RXD_W3_AMPDU … #define RXD_W3_DECRYPTED … #define RXD_W3_PLCP_SIGNAL … #define RXD_W3_PLCP_RSSI … unsigned int rt2800mmio_get_dma_done(struct data_queue *queue); /* TX descriptor initialization */ __le32 *rt2800mmio_get_txwi(struct queue_entry *entry); void rt2800mmio_write_tx_desc(struct queue_entry *entry, struct txentry_desc *txdesc); /* RX control handlers */ void rt2800mmio_fill_rxdone(struct queue_entry *entry, struct rxdone_entry_desc *rxdesc); /* Interrupt functions */ void rt2800mmio_txstatus_tasklet(struct tasklet_struct *t); void rt2800mmio_pretbtt_tasklet(struct tasklet_struct *t); void rt2800mmio_tbtt_tasklet(struct tasklet_struct *t); void rt2800mmio_rxdone_tasklet(struct tasklet_struct *t); void rt2800mmio_autowake_tasklet(struct tasklet_struct *t); irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance); void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev, enum dev_state state); /* Queue handlers */ void rt2800mmio_start_queue(struct data_queue *queue); void rt2800mmio_kick_queue(struct data_queue *queue); void rt2800mmio_flush_queue(struct data_queue *queue, bool drop); void rt2800mmio_stop_queue(struct data_queue *queue); void rt2800mmio_queue_init(struct data_queue *queue); /* Initialization functions */ int rt2800mmio_probe_hw(struct rt2x00_dev *rt2x00dev); bool rt2800mmio_get_entry_state(struct queue_entry *entry); void rt2800mmio_clear_entry(struct queue_entry *entry); int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev); int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev); /* Device state switch handlers. */ int rt2800mmio_enable_radio(struct rt2x00_dev *rt2x00dev); #endif /* RT2800MMIO_H */
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