/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. */ #ifndef __HW_H__ #define __HW_H__ #include <linux/seq_file.h> #include "viamode.h" #include "global.h" #include "via_modesetting.h" #define viafb_read_reg(p, i) … #define viafb_write_reg(i, p, d) … #define viafb_write_reg_mask(i, p, d, m) … /* VIA output devices */ #define VIA_LDVP0 … #define VIA_LDVP1 … #define VIA_DVP0 … #define VIA_CRT … #define VIA_DVP1 … #define VIA_LVDS1 … #define VIA_LVDS2 … /* VIA output device power states */ #define VIA_STATE_ON … #define VIA_STATE_STANDBY … #define VIA_STATE_SUSPEND … #define VIA_STATE_OFF … /* VIA output device sync polarity */ #define VIA_HSYNC_NEGATIVE … #define VIA_VSYNC_NEGATIVE … /**********************************************************/ /* Definition IGA2 Design Method of CRTC Shadow Registers */ /**********************************************************/ #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) … #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) … #define IGA2_VER_TOTAL_SHADOW_FORMULA(x) … #define IGA2_VER_ADDR_SHADOW_FORMULA(x) … #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) … #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) … #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) … #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) … /* Define Register Number for IGA2 Shadow CRTC Timing */ /* location: {CR6D,0,7},{CR71,3,3} */ #define IGA2_SHADOW_HOR_TOTAL_REG_NUM … /* location: {CR6E,0,7} */ #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM … /* location: {CR6F,0,7},{CR71,0,2} */ #define IGA2_SHADOW_VER_TOTAL_REG_NUM … /* location: {CR70,0,7},{CR71,4,6} */ #define IGA2_SHADOW_VER_ADDR_REG_NUM … /* location: {CR72,0,7},{CR74,4,6} */ #define IGA2_SHADOW_VER_BLANK_START_REG_NUM … /* location: {CR73,0,7},{CR74,0,2} */ #define IGA2_SHADOW_VER_BLANK_END_REG_NUM … /* location: {CR75,0,7},{CR76,4,6} */ #define IGA2_SHADOW_VER_SYNC_START_REG_NUM … /* location: {CR76,0,3} */ #define IGA2_SHADOW_VER_SYNC_END_REG_NUM … /* Define Fetch Count Register*/ /* location: {SR1C,0,7},{SR1D,0,1} */ #define IGA1_FETCH_COUNT_REG_NUM … /* 16 bytes alignment. */ #define IGA1_FETCH_COUNT_ALIGN_BYTE … /* x: H resolution, y: color depth */ #define IGA1_FETCH_COUNT_PATCH_VALUE … #define IGA1_FETCH_COUNT_FORMULA(x, y) … /* location: {CR65,0,7},{CR67,2,3} */ #define IGA2_FETCH_COUNT_REG_NUM … #define IGA2_FETCH_COUNT_ALIGN_BYTE … #define IGA2_FETCH_COUNT_PATCH_VALUE … #define IGA2_FETCH_COUNT_FORMULA(x, y) … /* Staring Address*/ /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */ #define IGA1_STARTING_ADDR_REG_NUM … /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */ #define IGA2_STARTING_ADDR_REG_NUM … /* Define Display OFFSET*/ /* These value are by HW suggested value*/ /* location: {SR17,0,7} */ #define K800_IGA1_FIFO_MAX_DEPTH … /* location: {SR16,0,5},{SR16,7,7} */ #define K800_IGA1_FIFO_THRESHOLD … /* location: {SR18,0,5},{SR18,7,7} */ #define K800_IGA1_FIFO_HIGH_THRESHOLD … /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */ /* because HW only 5 bits */ #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM … /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ #define K800_IGA2_FIFO_MAX_DEPTH … /* location: {CR68,0,3},{CR95,4,6} */ #define K800_IGA2_FIFO_THRESHOLD … /* location: {CR92,0,3},{CR95,0,2} */ #define K800_IGA2_FIFO_HIGH_THRESHOLD … /* location: {CR94,0,6} */ #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM … /* location: {SR17,0,7} */ #define P880_IGA1_FIFO_MAX_DEPTH … /* location: {SR16,0,5},{SR16,7,7} */ #define P880_IGA1_FIFO_THRESHOLD … /* location: {SR18,0,5},{SR18,7,7} */ #define P880_IGA1_FIFO_HIGH_THRESHOLD … /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */ /* because HW only 5 bits */ #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM … /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ #define P880_IGA2_FIFO_MAX_DEPTH … /* location: {CR68,0,3},{CR95,4,6} */ #define P880_IGA2_FIFO_THRESHOLD … /* location: {CR92,0,3},{CR95,0,2} */ #define P880_IGA2_FIFO_HIGH_THRESHOLD … /* location: {CR94,0,6} */ #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM … /* VT3314 chipset*/ /* location: {SR17,0,7} */ #define CN700_IGA1_FIFO_MAX_DEPTH … /* location: {SR16,0,5},{SR16,7,7} */ #define CN700_IGA1_FIFO_THRESHOLD … /* location: {SR18,0,5},{SR18,7,7} */ #define CN700_IGA1_FIFO_HIGH_THRESHOLD … /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero, because HW only 5 bits */ #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM … /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ #define CN700_IGA2_FIFO_MAX_DEPTH … /* location: {CR68,0,3},{CR95,4,6} */ #define CN700_IGA2_FIFO_THRESHOLD … /* location: {CR92,0,3},{CR95,0,2} */ #define CN700_IGA2_FIFO_HIGH_THRESHOLD … /* location: {CR94,0,6} */ #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM … /* For VT3324, these values are suggested by HW */ /* location: {SR17,0,7} */ #define CX700_IGA1_FIFO_MAX_DEPTH … /* location: {SR16,0,5},{SR16,7,7} */ #define CX700_IGA1_FIFO_THRESHOLD … /* location: {SR18,0,5},{SR18,7,7} */ #define CX700_IGA1_FIFO_HIGH_THRESHOLD … /* location: {SR22,0,4} */ #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM … /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ #define CX700_IGA2_FIFO_MAX_DEPTH … /* location: {CR68,0,3},{CR95,4,6} */ #define CX700_IGA2_FIFO_THRESHOLD … /* location: {CR92,0,3},{CR95,0,2} */ #define CX700_IGA2_FIFO_HIGH_THRESHOLD … /* location: {CR94,0,6} */ #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM … /* VT3336 chipset*/ /* location: {SR17,0,7} */ #define K8M890_IGA1_FIFO_MAX_DEPTH … /* location: {SR16,0,5},{SR16,7,7} */ #define K8M890_IGA1_FIFO_THRESHOLD … /* location: {SR18,0,5},{SR18,7,7} */ #define K8M890_IGA1_FIFO_HIGH_THRESHOLD … /* location: {SR22,0,4}. */ #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM … /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ #define K8M890_IGA2_FIFO_MAX_DEPTH … /* location: {CR68,0,3},{CR95,4,6} */ #define K8M890_IGA2_FIFO_THRESHOLD … /* location: {CR92,0,3},{CR95,0,2} */ #define K8M890_IGA2_FIFO_HIGH_THRESHOLD … /* location: {CR94,0,6} */ #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM … /* VT3327 chipset*/ /* location: {SR17,0,7} */ #define P4M890_IGA1_FIFO_MAX_DEPTH … /* location: {SR16,0,5},{SR16,7,7} */ #define P4M890_IGA1_FIFO_THRESHOLD … /* location: {SR18,0,5},{SR18,7,7} */ #define P4M890_IGA1_FIFO_HIGH_THRESHOLD … /* location: {SR22,0,4}. (32/4) =8 */ #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM … /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ #define P4M890_IGA2_FIFO_MAX_DEPTH … /* location: {CR68,0,3},{CR95,4,6} */ #define P4M890_IGA2_FIFO_THRESHOLD … /* location: {CR92,0,3},{CR95,0,2} */ #define P4M890_IGA2_FIFO_HIGH_THRESHOLD … /* location: {CR94,0,6} */ #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM … /* VT3364 chipset*/ /* location: {SR17,0,7} */ #define P4M900_IGA1_FIFO_MAX_DEPTH … /* location: {SR16,0,5},{SR16,7,7} */ #define P4M900_IGA1_FIFO_THRESHOLD … /* location: {SR18,0,5},{SR18,7,7} */ #define P4M900_IGA1_FIFO_HIGH_THRESHOLD … /* location: {SR22,0,4}. */ #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM … /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ #define P4M900_IGA2_FIFO_MAX_DEPTH … /* location: {CR68,0,3},{CR95,4,6} */ #define P4M900_IGA2_FIFO_THRESHOLD … /* location: {CR92,0,3},{CR95,0,2} */ #define P4M900_IGA2_FIFO_HIGH_THRESHOLD … /* location: {CR94,0,6} */ #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM … /* For VT3353, these values are suggested by HW */ /* location: {SR17,0,7} */ #define VX800_IGA1_FIFO_MAX_DEPTH … /* location: {SR16,0,5},{SR16,7,7} */ #define VX800_IGA1_FIFO_THRESHOLD … /* location: {SR18,0,5},{SR18,7,7} */ #define VX800_IGA1_FIFO_HIGH_THRESHOLD … /* location: {SR22,0,4} */ #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM … /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ #define VX800_IGA2_FIFO_MAX_DEPTH … /* location: {CR68,0,3},{CR95,4,6} */ #define VX800_IGA2_FIFO_THRESHOLD … /* location: {CR92,0,3},{CR95,0,2} */ #define VX800_IGA2_FIFO_HIGH_THRESHOLD … /* location: {CR94,0,6} */ #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM … /* For VT3409 */ #define VX855_IGA1_FIFO_MAX_DEPTH … #define VX855_IGA1_FIFO_THRESHOLD … #define VX855_IGA1_FIFO_HIGH_THRESHOLD … #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM … #define VX855_IGA2_FIFO_MAX_DEPTH … #define VX855_IGA2_FIFO_THRESHOLD … #define VX855_IGA2_FIFO_HIGH_THRESHOLD … #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM … /* For VT3410 */ #define VX900_IGA1_FIFO_MAX_DEPTH … #define VX900_IGA1_FIFO_THRESHOLD … #define VX900_IGA1_FIFO_HIGH_THRESHOLD … #define VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM … #define VX900_IGA2_FIFO_MAX_DEPTH … #define VX900_IGA2_FIFO_THRESHOLD … #define VX900_IGA2_FIFO_HIGH_THRESHOLD … #define VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM … #define IGA1_FIFO_DEPTH_SELECT_REG_NUM … #define IGA1_FIFO_THRESHOLD_REG_NUM … #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM … #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM … #define IGA2_FIFO_DEPTH_SELECT_REG_NUM … #define IGA2_FIFO_THRESHOLD_REG_NUM … #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM … #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM … #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) … #define IGA1_FIFO_THRESHOLD_FORMULA(x) … #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) … #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) … #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) … #define IGA2_FIFO_THRESHOLD_FORMULA(x) … #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) … #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) … /************************************************************************/ /* LCD Timing */ /************************************************************************/ /* 500 ms = 500000 us */ #define LCD_POWER_SEQ_TD0 … /* 50 ms = 50000 us */ #define LCD_POWER_SEQ_TD1 … /* 0 us */ #define LCD_POWER_SEQ_TD2 … /* 210 ms = 210000 us */ #define LCD_POWER_SEQ_TD3 … /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */ #define CLE266_POWER_SEQ_UNIT … /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */ #define K800_POWER_SEQ_UNIT … /* 2^13 * (1/14.31818M) = 572.1 us */ #define P880_POWER_SEQ_UNIT … #define CLE266_POWER_SEQ_FORMULA(x) … #define K800_POWER_SEQ_FORMULA(x) … #define P880_POWER_SEQ_FORMULA(x) … /* location: {CR8B,0,7},{CR8F,0,3} */ #define LCD_POWER_SEQ_TD0_REG_NUM … /* location: {CR8C,0,7},{CR8F,4,7} */ #define LCD_POWER_SEQ_TD1_REG_NUM … /* location: {CR8D,0,7},{CR90,0,3} */ #define LCD_POWER_SEQ_TD2_REG_NUM … /* location: {CR8E,0,7},{CR90,4,7} */ #define LCD_POWER_SEQ_TD3_REG_NUM … /* LCD Scaling factor*/ /* x: indicate setting horizontal size*/ /* y: indicate panel horizontal size*/ /* Horizontal scaling factor 10 bits (2^10) */ #define CLE266_LCD_HOR_SCF_FORMULA(x, y) … /* Vertical scaling factor 10 bits (2^10) */ #define CLE266_LCD_VER_SCF_FORMULA(x, y) … /* Horizontal scaling factor 10 bits (2^12) */ #define K800_LCD_HOR_SCF_FORMULA(x, y) … /* Vertical scaling factor 10 bits (2^11) */ #define K800_LCD_VER_SCF_FORMULA(x, y) … /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */ #define LCD_HOR_SCALING_FACTOR_REG_NUM … /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */ #define LCD_VER_SCALING_FACTOR_REG_NUM … /* location: {CR77,0,7},{CR79,4,5} */ #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE … /* location: {CR78,0,7},{CR79,6,7} */ #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE … struct io_register { … }; /***************************************************** ** Define IGA2 Shadow Display Timing **** *****************************************************/ /* IGA2 Shadow Horizontal Total */ struct iga2_shadow_hor_total { … }; /* IGA2 Shadow Horizontal Blank End */ struct iga2_shadow_hor_blank_end { … }; /* IGA2 Shadow Vertical Total */ struct iga2_shadow_ver_total { … }; /* IGA2 Shadow Vertical Addressable Video */ struct iga2_shadow_ver_addr { … }; /* IGA2 Shadow Vertical Blank Start */ struct iga2_shadow_ver_blank_start { … }; /* IGA2 Shadow Vertical Blank End */ struct iga2_shadow_ver_blank_end { … }; /* IGA2 Shadow Vertical Sync Start */ struct iga2_shadow_ver_sync_start { … }; /* IGA2 Shadow Vertical Sync End */ struct iga2_shadow_ver_sync_end { … }; /* IGA1 Fetch Count Register */ struct iga1_fetch_count { … }; /* IGA2 Fetch Count Register */ struct iga2_fetch_count { … }; struct fetch_count { … }; /* Starting Address Register */ struct iga1_starting_addr { … }; struct iga2_starting_addr { … }; struct starting_addr { … }; /* LCD Power Sequence Timer */ struct lcd_pwd_seq_td0 { … }; struct lcd_pwd_seq_td1 { … }; struct lcd_pwd_seq_td2 { … }; struct lcd_pwd_seq_td3 { … }; struct _lcd_pwd_seq_timer { … }; /* LCD Scaling Factor */ struct _lcd_hor_scaling_factor { … }; struct _lcd_ver_scaling_factor { … }; struct _lcd_scaling_factor { … }; struct pll_limit { … }; struct rgbLUT { … }; struct lcd_pwd_seq_timer { … }; /* Display FIFO Relation Registers*/ struct iga1_fifo_depth_select { … }; struct iga1_fifo_threshold_select { … }; struct iga1_fifo_high_threshold_select { … }; struct iga1_display_queue_expire_num { … }; struct iga2_fifo_depth_select { … }; struct iga2_fifo_threshold_select { … }; struct iga2_fifo_high_threshold_select { … }; struct iga2_display_queue_expire_num { … }; struct fifo_depth_select { … }; struct fifo_threshold_select { … }; struct fifo_high_threshold_select { … }; struct display_queue_expire_num { … }; struct iga2_shadow_crtc_timing { … }; /* device ID */ #define CLE266_FUNCTION3 … #define KM400_FUNCTION3 … #define CN400_FUNCTION2 … #define CN400_FUNCTION3 … /* support VT3314 chipset */ #define CN700_FUNCTION2 … #define CN700_FUNCTION3 … /* VT3324 chipset */ #define CX700_FUNCTION2 … #define CX700_FUNCTION3 … /* VT3204 chipset*/ #define KM800_FUNCTION3 … /* VT3336 chipset*/ #define KM890_FUNCTION3 … /* VT3327 chipset*/ #define P4M890_FUNCTION3 … /* VT3293 chipset*/ #define CN750_FUNCTION3 … /* VT3364 chipset*/ #define P4M900_FUNCTION3 … /* VT3353 chipset*/ #define VX800_FUNCTION3 … /* VT3409 chipset*/ #define VX855_FUNCTION3 … /* VT3410 chipset*/ #define VX900_FUNCTION3 … struct IODATA { … }; struct pci_device_id_info { … }; struct via_device_mapping { … }; extern int viafb_SAMM_ON; extern int viafb_dual_fb; extern int viafb_LCD2_ON; extern int viafb_LCD_ON; extern int viafb_DVI_ON; extern int viafb_hotplug; struct via_display_timing var_to_timing(const struct fb_var_screeninfo *var, u16 cxres, u16 cyres); void viafb_fill_crtc_timing(const struct fb_var_screeninfo *var, u16 cxres, u16 cyres, int iga); void viafb_set_vclock(u32 CLK, int set_iga); void viafb_load_reg(int timing_value, int viafb_load_reg_num, struct io_register *reg, int io_type); void via_set_source(u32 devices, u8 iga); void via_set_state(u32 devices, u8 state); void via_set_sync_polarity(u32 devices, u8 polarity); u32 via_parse_odev(char *input, char **end); void via_odev_to_seq(struct seq_file *m, u32 odev); void init_ad9389(void); /* Access I/O Function */ void viafb_lock_crt(void); void viafb_unlock_crt(void); void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga); void viafb_write_regx(struct io_reg RegTable[], int ItemNum); void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active); void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ *p_gfx_dpa_setting); int viafb_setmode(void); void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, const struct fb_videomode *mode); void viafb_init_chip_info(int chip_type); void viafb_init_dac(int set_iga); int viafb_get_refresh(int hres, int vres, u32 float_refresh); void viafb_update_device_setting(int hres, int vres, int bpp, int flag); void viafb_set_iga_path(void); void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue); void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue); void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len); #endif /* __HW_H__ */
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