/* * drivers/video/aty/radeon_base.c * * framebuffer driver for ATI Radeon chipset video boards * * Copyright 2003 Ben. Herrenschmidt <[email protected]> * Copyright 2000 Ani Joshi <[email protected]> * * i2c bits from Luca Tettamanti <[email protected]> * * Special thanks to ATI DevRel team for their hardware donations. * * ...Insert GPL boilerplate here... * * Significant portions of this driver apdated from XFree86 Radeon * driver which has the following copyright notice: * * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * XFree86 driver authors: * * Kevin E. Martin <[email protected]> * Rickard E. Faith <[email protected]> * Alan Hourihane <[email protected]> * */ #define RADEON_VERSION … #include "radeonfb.h" #include <linux/aperture.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/string.h> #include <linux/ctype.h> #include <linux/mm.h> #include <linux/slab.h> #include <linux/delay.h> #include <linux/time.h> #include <linux/fb.h> #include <linux/ioport.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/vmalloc.h> #include <linux/device.h> #include <asm/io.h> #include <linux/uaccess.h> #ifdef CONFIG_PPC #include "../macmodes.h" #ifdef CONFIG_BOOTX_TEXT #include <asm/btext.h> #endif #endif /* CONFIG_PPC */ #include <video/radeon.h> #include <linux/radeonfb.h> #include "../edid.h" // MOVE THAT TO include/video #include "ati_ids.h" #define MAX_MAPPED_VRAM … #define MIN_MAPPED_VRAM … #define CHIP_DEF(id, family, flags) … static const struct pci_device_id radeonfb_pci_table[] = …; MODULE_DEVICE_TABLE(pci, radeonfb_pci_table); reg_val; /* these common regs are cleared before mode setting so they do not * interfere with anything */ static reg_val common_regs[] = …; /* * globals */ static char *mode_option; static char *monitor_layout; static bool noaccel = …; static int default_dynclk = …; static bool nomodeset = …; static bool ignore_edid = …; static bool mirror = …; static int panel_yres = …; static bool force_dfp = …; static bool force_measure_pll = …; static bool nomtrr = …; static bool force_sleep; static bool ignore_devlist; static int backlight = … IS_BUILTIN(…); /* Note about this function: we have some rare cases where we must not schedule, * this typically happen with our special "wake up early" hook which allows us to * wake up the graphic chip (and thus get the console back) before everything else * on some machines that support that mechanism. At this point, interrupts are off * and scheduling is not permitted */ void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms) { … } void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo) { … } void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo) { … } void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask) { … } u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) { … } void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val) { … } void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, u32 val, u32 mask) { … } void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) { … } void radeon_engine_flush(struct radeonfb_info *rinfo) { … } void _radeon_engine_idle(struct radeonfb_info *rinfo) { … } static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) { … } static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) { … } #ifdef CONFIG_X86 static int radeon_find_mem_vbios(struct radeonfb_info *rinfo) { … } #endif #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) /* * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device * tree. Hopefully, ATI OF driver is kind enough to fill these */ static int radeon_read_xtal_OF(struct radeonfb_info *rinfo) { struct device_node *dp = rinfo->of_node; const u32 *val; if (dp == NULL) return -ENODEV; val = of_get_property(dp, "ATY,RefCLK", NULL); if (!val || !*val) { printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n"); return -EINVAL; } rinfo->pll.ref_clk = (*val) / 10; val = of_get_property(dp, "ATY,SCLK", NULL); if (val && *val) rinfo->pll.sclk = (*val) / 10; val = of_get_property(dp, "ATY,MCLK", NULL); if (val && *val) rinfo->pll.mclk = (*val) / 10; return 0; } #endif /* CONFIG_PPC || CONFIG_SPARC */ /* * Read PLL infos from chip registers */ static int radeon_probe_pll_params(struct radeonfb_info *rinfo) { … } /* * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...) */ static void radeon_get_pllinfo(struct radeonfb_info *rinfo) { … } static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info) { … } static int radeonfb_pan_display (struct fb_var_screeninfo *var, struct fb_info *info) { … } static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd, unsigned long arg) { … } int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch) { … } static int radeonfb_blank (int blank, struct fb_info *info) { … } static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct radeonfb_info *rinfo) { … } static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info) { … } static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info) { … } static void radeon_save_state (struct radeonfb_info *rinfo, struct radeon_regs *save) { … } static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) { … } /* * Timer function for delayed LVDS panel power up/down */ static void radeon_lvds_timer_func(struct timer_list *t) { … } /* * Apply a video mode. This will apply the whole register set, including * the PLL registers, to the card */ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, int regs_only) { … } /* * Calculate the PLL values for a given mode */ static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs, unsigned long freq) { … } static int radeonfb_set_par(struct fb_info *info) { … } static const struct fb_ops radeonfb_ops = …; static int radeon_set_fbinfo(struct radeonfb_info *rinfo) { … } /* * This reconfigure the card's internal memory map. In theory, we'd like * to setup the card's memory at the same address as it's PCI bus address, * and the AGP aperture right after that so that system RAM on 32 bits * machines at least, is directly accessible. However, doing so would * conflict with the current XFree drivers... * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree * on the proper way to set this up and duplicate this here. In the meantime, * I put the card's memory at 0 in card space and AGP at some random high * local (0xe0000000 for now) that will be changed by XFree/DRI anyway */ #ifdef CONFIG_PPC #undef SET_MC_FB_FROM_APERTURE static void fixup_memory_mappings(struct radeonfb_info *rinfo) { u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0; u32 save_crtc_ext_cntl; u32 aper_base, aper_size; u32 agp_base; /* First, we disable display to avoid interfering */ if (rinfo->has_CRTC2) { save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL); OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B); } save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL); save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL); OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS); OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B); mdelay(100); aper_base = INREG(CNFG_APER_0_BASE); aper_size = INREG(CNFG_APER_SIZE); #ifdef SET_MC_FB_FROM_APERTURE /* Set framebuffer to be at the same address as set in PCI BAR */ OUTREG(MC_FB_LOCATION, ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16)); rinfo->fb_local_base = aper_base; #else OUTREG(MC_FB_LOCATION, 0x7fff0000); rinfo->fb_local_base = 0; #endif agp_base = aper_base + aper_size; if (agp_base & 0xf0000000) agp_base = (aper_base | 0x0fffffff) + 1; /* Set AGP to be just after the framebuffer on a 256Mb boundary. This * assumes the FB isn't mapped to 0xf0000000 or above, but this is * always the case on PPCs afaik. */ #ifdef SET_MC_FB_FROM_APERTURE OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16)); #else OUTREG(MC_AGP_LOCATION, 0xffffe000); #endif /* Fixup the display base addresses & engine offsets while we * are at it as well */ #ifdef SET_MC_FB_FROM_APERTURE OUTREG(DISPLAY_BASE_ADDR, aper_base); if (rinfo->has_CRTC2) OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base); OUTREG(OV0_BASE_ADDR, aper_base); #else OUTREG(DISPLAY_BASE_ADDR, 0); if (rinfo->has_CRTC2) OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0); OUTREG(OV0_BASE_ADDR, 0); #endif mdelay(100); /* Restore display settings */ OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl); OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl); if (rinfo->has_CRTC2) OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl); pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n", aper_base, ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16), 0xffff0000 | (agp_base >> 16)); } #endif /* CONFIG_PPC */ static void radeon_identify_vram(struct radeonfb_info *rinfo) { … } /* * Sysfs */ static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid) { … } static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj, struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { … } static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj, struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { … } static const struct bin_attribute edid1_attr = …; static const struct bin_attribute edid2_attr = …; static int radeonfb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) { … } static void radeonfb_pci_unregister(struct pci_dev *pdev) { … } #ifdef CONFIG_PM #define RADEONFB_PCI_PM_OPS … #else #define RADEONFB_PCI_PM_OPS … #endif static struct pci_driver radeonfb_driver = …; #ifndef MODULE static int __init radeonfb_setup (char *options) { … } #endif /* MODULE */ static int __init radeonfb_init (void) { … } static void __exit radeonfb_exit (void) { … } module_init(…) …; module_exit(radeonfb_exit); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; module_param(noaccel, bool, 0); module_param(default_dynclk, int, 0); MODULE_PARM_DESC(…) …; MODULE_PARM_DESC(…) …; module_param(nomodeset, bool, 0); MODULE_PARM_DESC(…) …; module_param(mirror, bool, 0); MODULE_PARM_DESC(…) …; module_param(force_dfp, bool, 0); MODULE_PARM_DESC(…) …; module_param(ignore_edid, bool, 0); MODULE_PARM_DESC(…) …; module_param(monitor_layout, charp, 0); MODULE_PARM_DESC(…) …; module_param(force_measure_pll, bool, 0); MODULE_PARM_DESC(…) …; module_param(nomtrr, bool, 0); MODULE_PARM_DESC(…) …; module_param(panel_yres, int, 0); MODULE_PARM_DESC(…) …; module_param(mode_option, charp, 0); MODULE_PARM_DESC(…) …; #if defined(CONFIG_PM) && defined(CONFIG_X86) module_param(force_sleep, bool, 0); MODULE_PARM_DESC(…) …; module_param(ignore_devlist, bool, 0); MODULE_PARM_DESC(…) …; #endif
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