/* SPDX-License-Identifier: GPL-2.0-only */ /* * This file is part of wlcore * * Copyright (C) 2011 Texas Instruments Inc. */ #ifndef __WLCORE_H__ #define __WLCORE_H__ #include <linux/platform_device.h> #include "wlcore_i.h" #include "event.h" #include "boot.h" /* The maximum number of Tx descriptors in all chip families */ #define WLCORE_MAX_TX_DESCRIPTORS … /* * We always allocate this number of mac addresses. If we don't * have enough allocated addresses, the LAA bit is used */ #define WLCORE_NUM_MAC_ADDRESSES … /* wl12xx/wl18xx maximum transmission power (in dBm) */ #define WLCORE_MAX_TXPWR … /* Texas Instruments pre assigned OUI */ #define WLCORE_TI_OUI_ADDRESS … /* forward declaration */ struct wl1271_tx_hw_descr; enum wl_rx_buf_align; struct wl1271_rx_descriptor; struct wlcore_ops { … }; enum wlcore_partitions { … }; struct wlcore_partition { … }; struct wlcore_partition_set { … }; enum wlcore_registers { … }; struct wl1271_stats { … }; struct wl1271 { … }; int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev); void wlcore_remove(struct platform_device *pdev); struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size, u32 mbox_size); int wlcore_free_hw(struct wl1271 *wl); int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd, struct ieee80211_vif *vif, struct ieee80211_sta *sta, struct ieee80211_key_conf *key_conf); void wlcore_regdomain_config(struct wl1271 *wl); void wlcore_update_inconn_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif, struct wl1271_station *wl_sta, bool in_conn); static inline void wlcore_set_ht_cap(struct wl1271 *wl, enum nl80211_band band, struct ieee80211_sta_ht_cap *ht_cap) { … } /* Tell wlcore not to care about this element when checking the version */ #define WLCORE_FW_VER_IGNORE … static inline void wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip, unsigned int iftype_sr, unsigned int major_sr, unsigned int subtype_sr, unsigned int minor_sr, unsigned int iftype_mr, unsigned int major_mr, unsigned int subtype_mr, unsigned int minor_mr) { … } /* Firmware image load chunk size */ #define CHUNK_SIZE … /* Quirks */ /* Each RX/TX transaction requires an end-of-transaction transfer */ #define WLCORE_QUIRK_END_OF_TRANSACTION … /* wl127x and SPI don't support SDIO block size alignment */ #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN … /* means aggregated Rx packets are aligned to a SDIO block */ #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN … /* Older firmwares did not implement the FW logger over bus feature */ #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED … /* Older firmwares use an old NVS format */ #define WLCORE_QUIRK_LEGACY_NVS … /* pad only the last frame in the aggregate buffer */ #define WLCORE_QUIRK_TX_PAD_LAST_FRAME … /* extra header space is required for TKIP */ #define WLCORE_QUIRK_TKIP_HEADER_SPACE … /* Some firmwares not support sched scans while connected */ #define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN … /* separate probe response templates for one-shot and sched scans */ #define WLCORE_QUIRK_DUAL_PROBE_TMPL … /* Firmware requires reg domain configuration for active calibration */ #define WLCORE_QUIRK_REGDOMAIN_CONF … /* The FW only support a zero session id for AP */ #define WLCORE_QUIRK_AP_ZERO_SESSION_ID … /* TODO: move all these common registers and values elsewhere */ #define HW_ACCESS_ELP_CTRL_REG … /* ELP register commands */ #define ELPCTRL_WAKE_UP … #define ELPCTRL_WAKE_UP_WLAN_READY … #define ELPCTRL_SLEEP … /* ELP WLAN_READY bit */ #define ELPCTRL_WLAN_READY … /************************************************************************* Interrupt Trigger Register (Host -> WiLink) **************************************************************************/ /* Hardware to Embedded CPU Interrupts - first 32-bit register set */ /* * The host sets this bit to inform the Wlan * FW that a TX packet is in the XFER * Buffer #0. */ #define INTR_TRIG_TX_PROC0 … /* * The host sets this bit to inform the FW * that it read a packet from RX XFER * Buffer #0. */ #define INTR_TRIG_RX_PROC0 … #define INTR_TRIG_DEBUG_ACK … #define INTR_TRIG_STATE_CHANGED … /* Hardware to Embedded CPU Interrupts - second 32-bit register set */ /* * The host sets this bit to inform the FW * that it read a packet from RX XFER * Buffer #1. */ #define INTR_TRIG_RX_PROC1 … /* * The host sets this bit to inform the Wlan * hardware that a TX packet is in the XFER * Buffer #1. */ #define INTR_TRIG_TX_PROC1 … #define ACX_SLV_SOFT_RESET_BIT … #define SOFT_RESET_MAX_TIME … #define SOFT_RESET_STALL_TIME … #define ECPU_CONTROL_HALT … #define WELP_ARM_COMMAND_VAL … #endif /* __WLCORE_H__ */
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