/* SPDX-License-Identifier: GPL-2.0-only */ /* * This file is part of wl12xx * * Copyright (c) 1998-2007 Texas Instruments Incorporated * Copyright (C) 2008 Nokia Corporation */ #ifndef __REG_H__ #define __REG_H__ #include <linux/bitops.h> #define REGISTERS_BASE … #define DRPW_BASE … #define REGISTERS_DOWN_SIZE … #define REGISTERS_WORK_SIZE … #define HW_ACCESS_ELP_CTRL_REG_ADDR … /* ELP register commands */ #define ELPCTRL_WAKE_UP … #define ELPCTRL_WAKE_UP_WLAN_READY … #define ELPCTRL_SLEEP … /* ELP WLAN_READY bit */ #define ELPCTRL_WLAN_READY … /* Device Configuration registers*/ #define SOR_CFG … #define ECPU_CTRL … #define HI_CFG … /* EEPROM registers */ #define EE_START … #define EE_CTL … #define EE_DATA … #define EE_ADDR … #define EE_CTL_READ … #define CHIP_ID_B … #define CHIP_ID_1251_PG10 … #define CHIP_ID_1251_PG11 … #define CHIP_ID_1251_PG12 … #define ENABLE … /* Power Management registers */ #define ELP_CFG_MODE … #define ELP_CMD … #define PLL_CAL_TIME … #define CLK_REQ_TIME … #define CLK_BUF_TIME … #define CFG_PLL_SYNC_CNT … /* Scratch Pad registers*/ #define SCR_PAD0 … #define SCR_PAD1 … #define SCR_PAD2 … #define SCR_PAD3 … #define SCR_PAD4 … #define SCR_PAD4_SET … #define SCR_PAD4_CLR … #define SCR_PAD5 … #define SCR_PAD5_SET … #define SCR_PAD5_CLR … #define SCR_PAD6 … #define SCR_PAD7 … #define SCR_PAD8 … #define SCR_PAD9 … /* Spare registers*/ #define SPARE_A1 … #define SPARE_A2 … #define SPARE_A3 … #define SPARE_A4 … #define SPARE_A5 … #define SPARE_A6 … #define SPARE_A7 … #define SPARE_A8 … #define SPARE_B1 … #define SPARE_B2 … #define SPARE_B3 … #define SPARE_B4 … #define SPARE_B5 … #define SPARE_B6 … #define SPARE_B7 … #define SPARE_B8 … enum wl12xx_acx_int_reg { … }; #define ACX_SLV_SOFT_RESET_BIT … #define ACX_REG_EEPROM_START_BIT … /* Command/Information Mailbox Pointers */ /*=============================================== Command Mailbox Pointer - 32bit RW ------------------------------------------ This register holds the start address of the command mailbox located in the Wlan hardware memory. The host must read this pointer after a reset to find the location of the command mailbox. The Wlan hardware initializes the command mailbox pointer with the default address of the command mailbox. The command mailbox pointer is not valid until after the host receives the Init Complete interrupt from the Wlan hardware. ===============================================*/ #define REG_COMMAND_MAILBOX_PTR … /*=============================================== Information Mailbox Pointer - 32bit RW ------------------------------------------ This register holds the start address of the information mailbox located in the Wlan hardware memory. The host must read this pointer after a reset to find the location of the information mailbox. The Wlan hardware initializes the information mailbox pointer with the default address of the information mailbox. The information mailbox pointer is not valid until after the host receives the Init Complete interrupt from the Wlan hardware. ===============================================*/ #define REG_EVENT_MAILBOX_PTR … /* Misc */ #define REG_ENABLE_TX_RX … /* * Rx configuration (filter) information element * --------------------------------------------- */ #define REG_RX_CONFIG … #define REG_RX_FILTER … #define RX_CFG_ENABLE_PHY_HEADER_PLCP … /* promiscuous - receives all valid frames */ #define RX_CFG_PROMISCUOUS … /* receives frames from any BSSID */ #define RX_CFG_BSSID … /* receives frames destined to any MAC address */ #define RX_CFG_MAC … #define RX_CFG_ENABLE_ONLY_MY_DEST_MAC … #define RX_CFG_ENABLE_ANY_DEST_MAC … #define RX_CFG_ENABLE_ONLY_MY_BSSID … #define RX_CFG_ENABLE_ANY_BSSID … /* discards all broadcast frames */ #define RX_CFG_DISABLE_BCAST … #define RX_CFG_ENABLE_ONLY_MY_SSID … #define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR … #define RX_CFG_COPY_RX_STATUS … #define RX_CFG_TSF … #define RX_CONFIG_OPTION_ANY_DST_MY_BSS … #define RX_CONFIG_OPTION_MY_DST_ANY_BSS … #define RX_CONFIG_OPTION_ANY_DST_ANY_BSS … #define RX_CONFIG_OPTION_MY_DST_MY_BSS … #define RX_CONFIG_OPTION_FOR_SCAN … #define RX_CONFIG_OPTION_FOR_MEASUREMENT … #define RX_CONFIG_OPTION_FOR_JOIN … #define RX_CONFIG_OPTION_FOR_IBSS_JOIN … #define RX_FILTER_OPTION_DEF … #define RX_FILTER_OPTION_FILTER_ALL … #define RX_FILTER_OPTION_DEF_PRSP_BCN … #define RX_FILTER_OPTION_JOIN … /*=============================================== EEPROM Read/Write Request 32bit RW ------------------------------------------ 1 EE_READ - EEPROM Read Request 1 - Setting this bit loads a single byte of data into the EE_DATA register from the EEPROM location specified in the EE_ADDR register. The Wlan hardware hardware clears this bit automatically. EE_DATA is valid when this bit is cleared. 0 EE_WRITE - EEPROM Write Request - Setting this bit writes a single byte of data from the EE_DATA register into the EEPROM location specified in the EE_ADDR register. The Wlan hardware hardware clears this bit automatically. *===============================================*/ #define EE_CTL … #define ACX_EE_CTL_REG … #define EE_WRITE … #define EE_READ … /*=============================================== EEPROM Address - 32bit RW ------------------------------------------ This register specifies the address within the EEPROM from/to which to read/write data. ===============================================*/ #define EE_ADDR … #define ACX_EE_ADDR_REG … /*=============================================== EEPROM Data - 32bit RW ------------------------------------------ This register either holds the read 8 bits of data from the EEPROM or the write data to be written to the EEPROM. ===============================================*/ #define EE_DATA … #define ACX_EE_DATA_REG … #define EEPROM_ACCESS_TO … #define START_EEPROM_MGR … /*=============================================== EEPROM Base Address - 32bit RW ------------------------------------------ This register holds the upper nine bits [23:15] of the 24-bit Wlan hardware memory address for burst reads from EEPROM accesses. The EEPROM provides the lower 15 bits of this address. The MSB of the address from the EEPROM is ignored. ===============================================*/ #define ACX_EE_CFG … /*=============================================== GPIO Output Values -32bit, RW ------------------------------------------ [31:16] Reserved [15: 0] Specify the output values (at the output driver inputs) for GPIO[15:0], respectively. ===============================================*/ #define ACX_GPIO_OUT_REG … #define ACX_MAX_GPIO_LINES … /*=============================================== Contention window -32bit, RW ------------------------------------------ [31:26] Reserved [25:16] Max (0x3ff) [15:07] Reserved [06:00] Current contention window value - default is 0x1F ===============================================*/ #define ACX_CONT_WIND_CFG_REG … #define ACX_CONT_WIND_MIN_MASK … #define ACX_CONT_WIND_MAX … /*=============================================== HI_CFG Interface Configuration Register Values ------------------------------------------ ===============================================*/ #define HI_CFG_UART_ENABLE … #define HI_CFG_RST232_ENABLE … #define HI_CFG_CLOCK_REQ_SELECT … #define HI_CFG_HOST_INT_ENABLE … #define HI_CFG_VLYNQ_OUTPUT_ENABLE … #define HI_CFG_HOST_INT_ACTIVE_LOW … #define HI_CFG_UART_TX_OUT_GPIO_15 … #define HI_CFG_UART_TX_OUT_GPIO_14 … #define HI_CFG_UART_TX_OUT_GPIO_7 … /* * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile * for platforms using active high interrupt level */ #ifdef USE_ACTIVE_HIGH #define HI_CFG_DEF_VAL … #else #define HI_CFG_DEF_VAL … #endif #define REF_FREQ_19_2 … #define REF_FREQ_26_0 … #define REF_FREQ_38_4 … #define REF_FREQ_40_0 … #define REF_FREQ_33_6 … #define REF_FREQ_NUM … #define LUT_PARAM_INTEGER_DIVIDER … #define LUT_PARAM_FRACTIONAL_DIVIDER … #define LUT_PARAM_ATTN_BB … #define LUT_PARAM_ALPHA_BB … #define LUT_PARAM_STOP_TIME_BB … #define LUT_PARAM_BB_PLL_LOOP_FILTER … #define LUT_PARAM_NUM … #define ACX_EEPROMLESS_IND_REG … #define USE_EEPROM … #define SOFT_RESET_MAX_TIME … #define SOFT_RESET_STALL_TIME … #define NVS_DATA_BUNDARY_ALIGNMENT … /* Firmware image load chunk size */ #define CHUNK_SIZE … /* Firmware image header size */ #define FW_HDR_SIZE … #define ECPU_CONTROL_HALT … /****************************************************************************** CHANNELS, BAND & REG DOMAINS definitions ******************************************************************************/ enum { … }; enum { … }; enum { … }; enum { … }; #define SHORT_PREAMBLE_BIT … #define OFDM_RATE_BIT … #define PBCC_RATE_BIT … enum { … }; /****************************************************************************** Transmit-Descriptor RATE-SET field definitions... Define a new "Rate-Set" for TX path that incorporates the Rate & Modulation info into a single 16-bit field. TxdRateSet_t: b15 - Indicates Preamble type (1=SHORT, 0=LONG). Notes: Must be LONG (0) for 1Mbps rate. Does not apply (set to 0) for RevG-OFDM rates. b14 - Indicates PBCC encoding (1=PBCC, 0=not). Notes: Does not apply (set to 0) for rates 1 and 2 Mbps. Does not apply (set to 0) for RevG-OFDM rates. b13 - Unused (set to 0). b12-b0 - Supported Rate indicator bits as defined below. ******************************************************************************/ /************************************************************************* Interrupt Trigger Register (Host -> WiLink) **************************************************************************/ /* Hardware to Embedded CPU Interrupts - first 32-bit register set */ /* * Host Command Interrupt. Setting this bit masks * the interrupt that the host issues to inform * the FW that it has sent a command * to the Wlan hardware Command Mailbox. */ #define INTR_TRIG_CMD … /* * Host Event Acknowlegde Interrupt. The host * sets this bit to acknowledge that it received * the unsolicited information from the event * mailbox. */ #define INTR_TRIG_EVENT_ACK … /* * The host sets this bit to inform the Wlan * FW that a TX packet is in the XFER * Buffer #0. */ #define INTR_TRIG_TX_PROC0 … /* * The host sets this bit to inform the FW * that it read a packet from RX XFER * Buffer #0. */ #define INTR_TRIG_RX_PROC0 … #define INTR_TRIG_DEBUG_ACK … #define INTR_TRIG_STATE_CHANGED … /* Hardware to Embedded CPU Interrupts - second 32-bit register set */ /* * The host sets this bit to inform the FW * that it read a packet from RX XFER * Buffer #1. */ #define INTR_TRIG_RX_PROC1 … /* * The host sets this bit to inform the Wlan * hardware that a TX packet is in the XFER * Buffer #1. */ #define INTR_TRIG_TX_PROC1 … #endif
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