/* SPDX-License-Identifier: GPL-2.0-only */ /* * This file is part of wl1251 * * Copyright (c) 1998-2007 Texas Instruments Incorporated * Copyright (C) 2008 Nokia Corporation */ #ifndef __WL1251_TX_H__ #define __WL1251_TX_H__ #include <linux/bitops.h> #include "acx.h" /* * * TX PATH * * The Tx path uses a double buffer and a tx_control structure, each located * at a fixed address in the device's memory. On startup, the host retrieves * the pointers to these addresses. A double buffer allows for continuous data * flow towards the device. The host keeps track of which buffer is available * and alternates between these two buffers on a per packet basis. * * The size of each of the two buffers is large enough to hold the longest * 802.3 packet - maximum size Ethernet packet + header + descriptor. * TX complete indication will be received a-synchronously in a TX done cyclic * buffer which is composed of 16 tx_result descriptors structures and is used * in a cyclic manner. * * The TX (HOST) procedure is as follows: * 1. Read the Tx path status, that will give the data_out_count. * 2. goto 1, if not possible. * i.e. if data_in_count - data_out_count >= HwBuffer size (2 for double * buffer). * 3. Copy the packet (preceded by double_buffer_desc), if possible. * i.e. if data_in_count - data_out_count < HwBuffer size (2 for double * buffer). * 4. increment data_in_count. * 5. Inform the firmware by generating a firmware internal interrupt. * 6. FW will increment data_out_count after it reads the buffer. * * The TX Complete procedure: * 1. To get a TX complete indication the host enables the tx_complete flag in * the TX descriptor Structure. * 2. For each packet with a Tx Complete field set, the firmware adds the * transmit results to the cyclic buffer (txDoneRing) and sets both done_1 * and done_2 to 1 to indicate driver ownership. * 3. The firmware sends a Tx Complete interrupt to the host to trigger the * host to process the new data. Note: interrupt will be send per packet if * TX complete indication was requested in tx_control or per crossing * aggregation threshold. * 4. After receiving the Tx Complete interrupt, the host reads the * TxDescriptorDone information in a cyclic manner and clears both done_1 * and done_2 fields. * */ #define TX_COMPLETE_REQUIRED_BIT … #define TX_STATUS_DATA_OUT_COUNT_MASK … #define WL1251_TX_ALIGN_TO … #define WL1251_TX_ALIGN(len) … #define WL1251_TKIP_IV_SPACE … struct tx_control { … } __packed; struct tx_double_buffer_desc { … } __packed; enum { … }; struct tx_result { … } __packed; static inline int wl1251_tx_get_queue(int queue) { … } void wl1251_tx_work(struct work_struct *work); void wl1251_tx_complete(struct wl1251 *wl); void wl1251_tx_flush(struct wl1251 *wl); #endif
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