/* SPDX-License-Identifier: GPL-2.0-only */ /* * This file is part of wlcore * * Copyright (C) 2011 Texas Instruments Inc. */ #ifndef __REG_H__ #define __REG_H__ #define WL18XX_REGISTERS_BASE … #define WL18XX_CODE_BASE … #define WL18XX_DATA_BASE … #define WL18XX_DOUBLE_BUFFER_BASE … #define WL18XX_MCU_KEY_SEARCH_BASE … #define WL18XX_PHY_BASE … #define WL18XX_TOP_OCP_BASE … #define WL18XX_PACKET_RAM_BASE … #define WL18XX_HOST_BASE … #define WL18XX_REGISTERS_DOWN_SIZE … #define WL18XX_REG_BOOT_PART_START … #define WL18XX_REG_BOOT_PART_SIZE … #define WL18XX_PHY_INIT_MEM_ADDR … #define WL18XX_PHY_END_MEM_ADDR … #define WL18XX_PHY_INIT_MEM_SIZE … #define WL18XX_SDIO_WSPI_BASE … #define WL18XX_REG_CONFIG_BASE … #define WL18XX_WGCM_REGS_BASE … #define WL18XX_ENC_BASE … #define WL18XX_INTERRUPT_BASE … #define WL18XX_UART_BASE … #define WL18XX_WELP_BASE … #define WL18XX_TCP_CKSM_BASE … #define WL18XX_FIFO_BASE … #define WL18XX_OCP_BRIDGE_BASE … #define WL18XX_PMAC_RX_BASE … #define WL18XX_PMAC_ACM_BASE … #define WL18XX_PMAC_TX_BASE … #define WL18XX_PMAC_CSR_BASE … #define WL18XX_REG_ECPU_CONTROL … #define WL18XX_REG_INTERRUPT_NO_CLEAR … #define WL18XX_REG_INTERRUPT_ACK … #define WL18XX_REG_INTERRUPT_TRIG … #define WL18XX_REG_INTERRUPT_TRIG_H … #define WL18XX_REG_INTERRUPT_MASK … #define WL18XX_REG_CHIP_ID_B … #define WL18XX_SLV_MEM_DATA … #define WL18XX_SLV_REG_DATA … /* Scratch Pad registers*/ #define WL18XX_SCR_PAD0 … #define WL18XX_SCR_PAD1 … #define WL18XX_SCR_PAD2 … #define WL18XX_SCR_PAD3 … #define WL18XX_SCR_PAD4 … #define WL18XX_SCR_PAD4_SET … #define WL18XX_SCR_PAD4_CLR … #define WL18XX_SCR_PAD5 … #define WL18XX_SCR_PAD5_SET … #define WL18XX_SCR_PAD5_CLR … #define WL18XX_SCR_PAD6 … #define WL18XX_SCR_PAD7 … #define WL18XX_SCR_PAD8 … #define WL18XX_SCR_PAD9 … /* Spare registers*/ #define WL18XX_SPARE_A1 … #define WL18XX_SPARE_A2 … #define WL18XX_SPARE_A3 … #define WL18XX_SPARE_A4 … #define WL18XX_SPARE_A5 … #define WL18XX_SPARE_A6 … #define WL18XX_SPARE_A7 … #define WL18XX_SPARE_A8 … #define WL18XX_SPARE_B1 … #define WL18XX_SPARE_B2 … #define WL18XX_SPARE_B3 … #define WL18XX_SPARE_B4 … #define WL18XX_SPARE_B5 … #define WL18XX_SPARE_B6 … #define WL18XX_SPARE_B7 … #define WL18XX_SPARE_B8 … #define WL18XX_REG_COMMAND_MAILBOX_PTR … #define WL18XX_REG_EVENT_MAILBOX_PTR … #define WL18XX_EEPROMLESS_IND … #define WL18XX_WELP_ARM_COMMAND … #define WL18XX_ENABLE … #define TOP_FN0_CCCR_REG_32 … /* PRCM registers */ #define PLATFORM_DETECTION … #define OCS_EN … #define PRIMARY_CLK_DETECT … #define PLLSH_COEX_PLL_N … #define PLLSH_COEX_PLL_M … #define PLLSH_COEX_PLL_SWALLOW_EN … #define PLLSH_WL_PLL_SEL … #define PLLSH_WCS_PLL_N … #define PLLSH_WCS_PLL_M … #define PLLSH_WCS_PLL_Q_FACTOR_CFG_1 … #define PLLSH_WCS_PLL_Q_FACTOR_CFG_2 … #define PLLSH_WCS_PLL_P_FACTOR_CFG_1 … #define PLLSH_WCS_PLL_P_FACTOR_CFG_2 … #define PLLSH_WCS_PLL_SWALLOW_EN … #define PLLSH_WL_PLL_EN … #define PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK … #define PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK … #define PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK … #define PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK … #define PLLSH_WL_PLL_EN_VAL1 … #define PLLSH_WL_PLL_EN_VAL2 … #define PLLSH_COEX_PLL_SWALLOW_EN_VAL1 … #define PLLSH_COEX_PLL_SWALLOW_EN_VAL2 … #define PLLSH_WCS_PLL_SWALLOW_EN_VAL1 … #define PLLSH_WCS_PLL_SWALLOW_EN_VAL2 … #define PLLSH_WL_PLL_SEL_WCS_PLL … #define PLLSH_WL_PLL_SEL_COEX_PLL … #define WL18XX_REG_FUSE_DATA_1_3 … #define WL18XX_PG_VER_MASK … #define WL18XX_PG_VER_OFFSET … #define WL18XX_ROM_VER_MASK … #define WL18XX_ROM_VER_OFFSET … #define WL18XX_METAL_VER_MASK … #define WL18XX_METAL_VER_OFFSET … #define WL18XX_NEW_METAL_VER_MASK … #define WL18XX_NEW_METAL_VER_OFFSET … #define WL18XX_PACKAGE_TYPE_OFFSET … #define WL18XX_PACKAGE_TYPE_WSP … #define WL18XX_REG_FUSE_DATA_2_3 … #define WL18XX_RDL_VER_MASK … #define WL18XX_RDL_VER_OFFSET … #define WL18XX_REG_FUSE_BD_ADDR_1 … #define WL18XX_REG_FUSE_BD_ADDR_2 … #define WL18XX_CMD_MBOX_ADDRESS … #define WL18XX_FW_STATUS_ADDR … #define CHIP_ID_185x_PG10 … #define CHIP_ID_185x_PG20 … /* * Host Command Interrupt. Setting this bit masks * the interrupt that the host issues to inform * the FW that it has sent a command * to the Wlan hardware Command Mailbox. */ #define WL18XX_INTR_TRIG_CMD … /* * Host Event Acknowlegde Interrupt. The host * sets this bit to acknowledge that it received * the unsolicited information from the event * mailbox. */ #define WL18XX_INTR_TRIG_EVENT_ACK … /* * To boot the firmware in PLT mode we need to write this value in * SCR_PAD8 before starting. */ #define WL18XX_SCR_PAD8_PLT … enum { … }; enum { … }; enum { … }; enum wl18xx_rdl_num { … }; /* FPGA_SPARE_1 register - used to change the PHY ATPG clock at boot time */ #define WL18XX_PHY_FPGA_SPARE_1 … /* command to disable FDSP clock */ #define MEM_FDSP_CLK_120_DISABLE … /* command to set ATPG clock toward FDSP Code RAM rather than its own clock */ #define MEM_FDSP_CODERAM_FUNC_CLK_SEL … /* command to re-enable FDSP clock */ #define MEM_FDSP_CLK_120_ENABLE … #endif /* __REG_H__ */
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