/* SPDX-License-Identifier: GPL-2.0-or-later */ /* ZD1211 USB-WLAN driver for Linux * * Copyright (C) 2005-2007 Ulrich Kunitz <[email protected]> * Copyright (C) 2006-2007 Daniel Drake <[email protected]> */ #ifndef _ZD_CHIP_H #define _ZD_CHIP_H #include <net/mac80211.h> #include "zd_rf.h" #include "zd_usb.h" /* Header for the Media Access Controller (MAC) and the Baseband Processor * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and * adds a processor for handling the USB protocol. */ /* Address space */ enum { … }; #define CTL_REG(offset) … #define E2P_DATA(offset) … #define FWRAW_DATA(offset) … /* 8-bit hardware registers */ #define ZD_CR0 … #define ZD_CR1 … #define ZD_CR2 … #define ZD_CR3 … #define ZD_CR5 … /* bit 5: if set short preamble used * bit 6: filter band - Japan channel 14 on, else off */ #define ZD_CR6 … #define ZD_CR7 … #define ZD_CR8 … #define ZD_CR4 … #define ZD_CR9 … /* bit 2: antenna switch (together with ZD_CR10) */ #define ZD_CR10 … /* bit 1: antenna switch (together with ZD_CR9) * RF2959 controls with ZD_CR11 radion on and off */ #define ZD_CR11 … /* bit 6: TX power control for OFDM * RF2959 controls with ZD_CR10 radio on and off */ #define ZD_CR12 … #define ZD_CR13 … #define ZD_CR14 … #define ZD_CR15 … #define ZD_CR16 … #define ZD_CR17 … #define ZD_CR18 … #define ZD_CR19 … #define ZD_CR20 … #define ZD_CR21 … #define ZD_CR22 … #define ZD_CR23 … #define ZD_CR24 … #define ZD_CR25 … #define ZD_CR26 … #define ZD_CR27 … #define ZD_CR28 … #define ZD_CR29 … #define ZD_CR30 … #define ZD_CR31 … #define ZD_CR32 … #define ZD_CR33 … #define ZD_CR34 … #define ZD_CR35 … #define ZD_CR36 … #define ZD_CR37 … #define ZD_CR38 … #define ZD_CR39 … #define ZD_CR40 … #define ZD_CR41 … #define ZD_CR42 … #define ZD_CR43 … #define ZD_CR44 … #define ZD_CR45 … #define ZD_CR46 … #define ZD_CR47 … #define ZD_CR48 … #define ZD_CR49 … #define ZD_CR50 … #define ZD_CR51 … #define ZD_CR52 … #define ZD_CR53 … #define ZD_CR54 … #define ZD_CR55 … #define ZD_CR56 … #define ZD_CR57 … #define ZD_CR58 … #define ZD_CR59 … #define ZD_CR60 … #define ZD_CR61 … #define ZD_CR62 … #define ZD_CR63 … #define ZD_CR64 … #define ZD_CR65 … #define ZD_CR66 … #define ZD_CR67 … #define ZD_CR68 … #define ZD_CR69 … #define ZD_CR70 … #define ZD_CR71 … #define ZD_CR72 … #define ZD_CR73 … #define ZD_CR74 … #define ZD_CR75 … #define ZD_CR76 … #define ZD_CR77 … #define ZD_CR78 … #define ZD_CR79 … #define ZD_CR80 … #define ZD_CR81 … #define ZD_CR82 … #define ZD_CR83 … #define ZD_CR84 … #define ZD_CR85 … #define ZD_CR86 … #define ZD_CR87 … #define ZD_CR88 … #define ZD_CR89 … #define ZD_CR90 … #define ZD_CR91 … #define ZD_CR92 … #define ZD_CR93 … #define ZD_CR94 … #define ZD_CR95 … #define ZD_CR96 … #define ZD_CR97 … #define ZD_CR98 … #define ZD_CR99 … #define ZD_CR100 … #define ZD_CR101 … #define ZD_CR102 … #define ZD_CR103 … #define ZD_CR104 … #define ZD_CR105 … #define ZD_CR106 … #define ZD_CR107 … #define ZD_CR108 … #define ZD_CR109 … #define ZD_CR110 … #define ZD_CR111 … #define ZD_CR112 … #define ZD_CR113 … #define ZD_CR114 … #define ZD_CR115 … #define ZD_CR116 … #define ZD_CR117 … #define ZD_CR118 … #define ZD_CR119 … #define ZD_CR120 … #define ZD_CR121 … #define ZD_CR122 … #define ZD_CR123 … #define ZD_CR124 … #define ZD_CR125 … #define ZD_CR126 … #define ZD_CR127 … #define ZD_CR128 … #define ZD_CR129 … #define ZD_CR130 … #define ZD_CR131 … #define ZD_CR132 … #define ZD_CR133 … #define ZD_CR134 … #define ZD_CR135 … #define ZD_CR136 … #define ZD_CR137 … #define ZD_CR138 … #define ZD_CR139 … #define ZD_CR140 … #define ZD_CR141 … #define ZD_CR142 … #define ZD_CR143 … #define ZD_CR144 … #define ZD_CR145 … #define ZD_CR146 … #define ZD_CR147 … #define ZD_CR148 … #define ZD_CR149 … #define ZD_CR150 … #define ZD_CR151 … #define ZD_CR152 … #define ZD_CR153 … #define ZD_CR154 … #define ZD_CR155 … #define ZD_CR156 … #define ZD_CR157 … #define ZD_CR158 … #define ZD_CR159 … #define ZD_CR160 … #define ZD_CR161 … #define ZD_CR162 … #define ZD_CR163 … #define ZD_CR164 … #define ZD_CR165 … #define ZD_CR166 … #define ZD_CR167 … #define ZD_CR168 … #define ZD_CR169 … #define ZD_CR170 … #define ZD_CR171 … #define ZD_CR172 … #define ZD_CR173 … #define ZD_CR174 … #define ZD_CR175 … #define ZD_CR176 … #define ZD_CR177 … #define ZD_CR178 … #define ZD_CR179 … #define ZD_CR180 … #define ZD_CR181 … #define ZD_CR182 … #define ZD_CR183 … #define ZD_CR184 … #define ZD_CR185 … #define ZD_CR186 … #define ZD_CR187 … #define ZD_CR188 … #define ZD_CR189 … #define ZD_CR190 … #define ZD_CR191 … #define ZD_CR192 … #define ZD_CR193 … #define ZD_CR194 … #define ZD_CR195 … #define ZD_CR196 … #define ZD_CR197 … #define ZD_CR198 … #define ZD_CR199 … #define ZD_CR200 … #define ZD_CR201 … #define ZD_CR202 … #define ZD_CR203 … #define ZD_CR204 … #define ZD_CR205 … #define ZD_CR206 … #define ZD_CR207 … #define ZD_CR208 … #define ZD_CR209 … #define ZD_CR210 … #define ZD_CR211 … #define ZD_CR212 … #define ZD_CR213 … #define ZD_CR214 … #define ZD_CR215 … #define ZD_CR216 … #define ZD_CR217 … #define ZD_CR218 … #define ZD_CR219 … #define ZD_CR220 … #define ZD_CR221 … #define ZD_CR222 … #define ZD_CR223 … #define ZD_CR224 … #define ZD_CR225 … #define ZD_CR226 … #define ZD_CR227 … #define ZD_CR228 … #define ZD_CR229 … #define ZD_CR230 … #define ZD_CR231 … #define ZD_CR232 … #define ZD_CR233 … #define ZD_CR234 … #define ZD_CR235 … #define ZD_CR236 … #define ZD_CR240 … /* bit 7: host-controlled RF register writes * ZD_CR241-ZD_CR245: for hardware controlled writing of RF bits, not needed for * USB */ #define ZD_CR241 … #define ZD_CR242 … #define ZD_CR243 … #define ZD_CR244 … #define ZD_CR245 … #define ZD_CR251 … #define ZD_CR252 … #define ZD_CR253 … #define ZD_CR254 … #define ZD_CR255 … #define CR_MAX_PHY_REG … /* Taken from the ZYDAS driver, not all of them are relevant for the ZD1211 * driver. */ #define CR_RF_IF_CLK … #define CR_RF_IF_DATA … #define CR_PE1_PE2 … #define CR_PE2_DLY … #define CR_LE1 … #define CR_LE2 … /* Seems to enable/disable GPI (General Purpose IO?) */ #define CR_GPI_EN … #define CR_RADIO_PD … #define CR_RF2948_PD … #define CR_ENABLE_PS_MANUAL_AGC … #define CR_CONFIG_PHILIPS … #define CR_SA2400_SER_AP … #define CR_I2C_WRITE … #define CR_SA2400_SER_RP … #define CR_RADIO_PE … #define CR_RST_BUS_MASTER … #define CR_RFCFG … #define CR_HSTSCHG … #define CR_PHY_ON … #define CR_RX_DELAY … #define CR_RX_PE_DELAY … #define CR_GPIO_1 … #define CR_GPIO_2 … #define CR_EncryBufMux … #define CR_PS_CTRL … #define CR_ADDA_PWR_DWN … #define CR_ADDA_MBIAS_WARMTIME … #define CR_MAC_PS_STATE … #define CR_INTERRUPT … #define INT_TX_COMPLETE … #define INT_RX_COMPLETE … #define INT_RETRY_FAIL … #define INT_WAKEUP … #define INT_DTIM_NOTIFY … #define INT_CFG_NEXT_BCN … #define INT_BUS_ABORT … #define INT_TX_FIFO_READY … #define INT_UART … #define INT_TX_COMPLETE_EN … #define INT_RX_COMPLETE_EN … #define INT_RETRY_FAIL_EN … #define INT_WAKEUP_EN … #define INT_DTIM_NOTIFY_EN … #define INT_CFG_NEXT_BCN_EN … #define INT_BUS_ABORT_EN … #define INT_TX_FIFO_READY_EN … #define INT_UART_EN … #define CR_TSF_LOW_PART … #define CR_TSF_HIGH_PART … /* Following three values are in time units (1024us) * Following condition must be met: * atim < tbtt < bcn */ #define CR_ATIM_WND_PERIOD … #define CR_BCN_INTERVAL … #define CR_PRE_TBTT … /* in units of TU(1024us) */ /* for UART support */ #define CR_UART_RBR_THR_DLL … #define CR_UART_DLM_IER … #define CR_UART_IIR_FCR … #define CR_UART_LCR … #define CR_UART_MCR … #define CR_UART_LSR … #define CR_UART_MSR … #define CR_UART_ECR … #define CR_UART_STATUS … #define CR_PCI_TX_ADDR_P1 … #define CR_PCI_TX_AddR_P2 … #define CR_PCI_RX_AddR_P1 … #define CR_PCI_RX_AddR_P2 … /* must be overwritten if custom MAC address will be used */ #define CR_MAC_ADDR_P1 … #define CR_MAC_ADDR_P2 … #define CR_BSSID_P1 … #define CR_BSSID_P2 … #define CR_BCN_PLCP_CFG … /* Group hash table for filtering incoming packets. * * The group hash table is 64 bit large and split over two parts. The first * part is the lower part. The upper 6 bits of the last byte of the target * address are used as index. Packets are received if the hash table bit is * set. This is used for multicast handling, but for broadcasts (address * ff:ff:ff:ff:ff:ff) the highest bit in the second table must also be set. */ #define CR_GROUP_HASH_P1 … #define CR_GROUP_HASH_P2 … #define CR_RX_TIMEOUT … /* Basic rates supported by the BSS. When producing ACK or CTS messages, the * device will use a rate in this table that is less than or equal to the rate * of the incoming frame which prompted the response. */ #define CR_BASIC_RATE_TBL … #define CR_RATE_1M … #define CR_RATE_2M … #define CR_RATE_5_5M … #define CR_RATE_11M … #define CR_RATE_6M … #define CR_RATE_9M … #define CR_RATE_12M … #define CR_RATE_18M … #define CR_RATE_24M … #define CR_RATE_36M … #define CR_RATE_48M … #define CR_RATE_54M … #define CR_RATES_80211G … #define CR_RATES_80211B … /* Mandatory rates required in the BSS. When producing ACK or CTS messages, if * the device could not find an appropriate rate in CR_BASIC_RATE_TBL, it will * look for a rate in this table that is less than or equal to the rate of * the incoming frame. */ #define CR_MANDATORY_RATE_TBL … #define CR_RTS_CTS_RATE … /* These are all bit indexes in CR_RTS_CTS_RATE, so remember to shift. */ #define RTSCTS_SH_RTS_RATE … #define RTSCTS_SH_EXP_CTS_RATE … #define RTSCTS_SH_RTS_MOD_TYPE … #define RTSCTS_SH_RTS_PMB_TYPE … #define RTSCTS_SH_CTS_RATE … #define RTSCTS_SH_CTS_MOD_TYPE … #define RTSCTS_SH_CTS_PMB_TYPE … #define CR_WEP_PROTECT … #define CR_RX_THRESHOLD … /* register for controlling the LEDS */ #define CR_LED … /* masks for controlling LEDs */ #define LED1 … #define LED2 … #define LED_SW … /* Seems to indicate that the configuration is over. */ #define CR_AFTER_PNP … #define CR_ACK_TIME_80211 … #define CR_RX_OFFSET … #define CR_BCN_LENGTH … #define CR_PHY_DELAY … #define CR_BCN_FIFO … #define CR_SNIFFER_ON … #define CR_ENCRYPTION_TYPE … #define NO_WEP … #define WEP64 … #define WEP128 … #define WEP256 … #define ENC_SNIFFER … #define CR_ZD1211_RETRY_MAX … #define CR_REG1 … /* Setting the bit UNLOCK_PHY_REGS disallows the write access to physical * registers, so one could argue it is a LOCK bit. But calling it * LOCK_PHY_REGS makes it confusing. */ #define UNLOCK_PHY_REGS … #define CR_DEVICE_STATE … #define CR_UNDERRUN_CNT … #define CR_RX_FILTER … #define RX_FILTER_ASSOC_REQUEST … #define RX_FILTER_ASSOC_RESPONSE … #define RX_FILTER_REASSOC_REQUEST … #define RX_FILTER_REASSOC_RESPONSE … #define RX_FILTER_PROBE_REQUEST … #define RX_FILTER_PROBE_RESPONSE … /* bits 6 and 7 reserved */ #define RX_FILTER_BEACON … #define RX_FILTER_ATIM … #define RX_FILTER_DISASSOC … #define RX_FILTER_AUTH … #define RX_FILTER_DEAUTH … #define RX_FILTER_PSPOLL … #define RX_FILTER_RTS … #define RX_FILTER_CTS … #define RX_FILTER_ACK … #define RX_FILTER_CFEND … #define RX_FILTER_CFACK … /* Enable bits for all frames you are interested in. */ #define STA_RX_FILTER … #define RX_FILTER_CTRL … #define BCN_MODE_AP … #define BCN_MODE_IBSS … /* Monitor mode sets filter to 0xfffff */ #define CR_ACK_TIMEOUT_EXT … #define CR_BCN_FIFO_SEMAPHORE … #define CR_IFS_VALUE … #define IFS_VALUE_DIFS_SH … #define IFS_VALUE_EIFS_SH … #define IFS_VALUE_SIFS_SH … #define IFS_VALUE_DEFAULT … #define CR_RX_TIME_OUT … #define CR_TOTAL_RX_FRM … #define CR_CRC32_CNT … #define CR_CRC16_CNT … #define CR_DECRYPTION_ERR_UNI … #define CR_RX_FIFO_OVERRUN … #define CR_DECRYPTION_ERR_MUL … #define CR_NAV_CNT … #define CR_NAV_CCA … #define CR_RETRY_CNT … #define CR_READ_TCB_ADDR … #define CR_READ_RFD_ADDR … #define CR_CWMIN_CWMAX … #define CR_TOTAL_TX_FRM … /* CAM: Continuous Access Mode (power management) */ #define CR_CAM_MODE … #define MODE_IBSS … #define MODE_AP … #define MODE_STA … #define MODE_AP_WDS … #define CR_CAM_ROLL_TB_LOW … #define CR_CAM_ROLL_TB_HIGH … #define CR_CAM_ADDRESS … #define CR_CAM_DATA … #define CR_ROMDIR … #define CR_DECRY_ERR_FLG_LOW … #define CR_DECRY_ERR_FLG_HIGH … #define CR_WEPKEY0 … #define CR_WEPKEY1 … #define CR_WEPKEY2 … #define CR_WEPKEY3 … #define CR_WEPKEY4 … #define CR_WEPKEY5 … #define CR_WEPKEY6 … #define CR_WEPKEY7 … #define CR_WEPKEY8 … #define CR_WEPKEY9 … #define CR_WEPKEY10 … #define CR_WEPKEY11 … #define CR_WEPKEY12 … #define CR_WEPKEY13 … #define CR_WEPKEY14 … #define CR_WEPKEY15 … #define CR_TKIP_MODE … #define CR_EEPROM_PROTECT0 … #define CR_EEPROM_PROTECT1 … #define CR_DBG_FIFO_RD … #define CR_DBG_SELECT … #define CR_FIFO_Length … #define CR_RSSI_MGC … #define CR_PON … #define CR_RX_ON … #define CR_TX_ON … #define CR_CHIP_EN … #define CR_LO_SW … #define CR_TXRX_SW … #define CR_S_MD … #define CR_USB_DEBUG_PORT … #define CR_ZD1211B_CWIN_MAX_MIN_AC0 … #define CR_ZD1211B_CWIN_MAX_MIN_AC1 … #define CR_ZD1211B_CWIN_MAX_MIN_AC2 … #define CR_ZD1211B_CWIN_MAX_MIN_AC3 … #define CR_ZD1211B_AIFS_CTL1 … #define CR_ZD1211B_AIFS_CTL2 … #define CR_ZD1211B_TXOP … #define CR_ZD1211B_RETRY_MAX … /* Value for CR_ZD1211_RETRY_MAX & CR_ZD1211B_RETRY_MAX. Vendor driver uses 2, * we use 0. The first rate is tried (count+2), then all next rates are tried * twice, until 1 Mbits is tried. */ #define ZD1211_RETRY_COUNT … #define ZD1211B_RETRY_COUNT … /* Used to detect PLL lock */ #define UW2453_INTR_REG … #define CWIN_SIZE … #define HWINT_ENABLED … #define HWINT_DISABLED … #define E2P_PWR_INT_GUARD … #define E2P_CHANNEL_COUNT … /* If you compare this addresses with the ZYDAS orignal driver, please notify * that we use word mapping for the EEPROM. */ /* * Upper 16 bit contains the regulatory domain. */ #define E2P_SUBID … #define E2P_POD … #define E2P_MAC_ADDR_P1 … #define E2P_MAC_ADDR_P2 … #define E2P_PWR_CAL_VALUE1 … #define E2P_PWR_CAL_VALUE2 … #define E2P_PWR_CAL_VALUE3 … #define E2P_PWR_CAL_VALUE4 … #define E2P_PWR_INT_VALUE1 … #define E2P_PWR_INT_VALUE2 … #define E2P_PWR_INT_VALUE3 … #define E2P_PWR_INT_VALUE4 … /* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30) * also only 11 channels. */ #define E2P_ALLOWED_CHANNEL … #define E2P_DEVICE_VER … #define E2P_PHY_REG … #define E2P_36M_CAL_VALUE1 … #define E2P_36M_CAL_VALUE2 … #define E2P_36M_CAL_VALUE3 … #define E2P_36M_CAL_VALUE4 … #define E2P_11A_INT_VALUE1 … #define E2P_11A_INT_VALUE2 … #define E2P_11A_INT_VALUE3 … #define E2P_11A_INT_VALUE4 … #define E2P_48M_CAL_VALUE1 … #define E2P_48M_CAL_VALUE2 … #define E2P_48M_CAL_VALUE3 … #define E2P_48M_CAL_VALUE4 … #define E2P_48M_INT_VALUE1 … #define E2P_48M_INT_VALUE2 … #define E2P_48M_INT_VALUE3 … #define E2P_48M_INT_VALUE4 … #define E2P_54M_CAL_VALUE1 … #define E2P_54M_CAL_VALUE2 … #define E2P_54M_CAL_VALUE3 … #define E2P_54M_CAL_VALUE4 … #define E2P_54M_INT_VALUE1 … #define E2P_54M_INT_VALUE2 … #define E2P_54M_INT_VALUE3 … #define E2P_54M_INT_VALUE4 … /* This word contains the base address of the FW_REG_ registers below */ #define FWRAW_REGS_ADDR … /* All 16 bit values, offset from the address in FWRAW_REGS_ADDR */ enum { … }; /* Values for FW_LINK_STATUS */ #define FW_LINK_OFF … #define FW_LINK_TX … /* 0x2 - link led on? */ enum { … }; struct zd_chip { … }; static inline struct zd_chip *zd_usb_to_chip(struct zd_usb *usb) { … } static inline struct zd_chip *zd_rf_to_chip(struct zd_rf *rf) { … } #define zd_chip_dev(chip) … void zd_chip_init(struct zd_chip *chip, struct ieee80211_hw *hw, struct usb_interface *intf); void zd_chip_clear(struct zd_chip *chip); int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr); int zd_chip_init_hw(struct zd_chip *chip); int zd_chip_reset(struct zd_chip *chip); static inline int zd_chip_is_zd1211b(struct zd_chip *chip) { … } static inline int zd_ioread16v_locked(struct zd_chip *chip, u16 *values, const zd_addr_t *addresses, unsigned int count) { … } static inline int zd_ioread16_locked(struct zd_chip *chip, u16 *value, const zd_addr_t addr) { … } int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addresses, unsigned int count); static inline int zd_ioread32_locked(struct zd_chip *chip, u32 *value, const zd_addr_t addr) { … } static inline int zd_iowrite16_locked(struct zd_chip *chip, u16 value, zd_addr_t addr) { … } int zd_iowrite16a_locked(struct zd_chip *chip, const struct zd_ioreq16 *ioreqs, unsigned int count); int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, unsigned int count); static inline int zd_iowrite32_locked(struct zd_chip *chip, u32 value, zd_addr_t addr) { … } int zd_iowrite32a_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, unsigned int count); static inline int zd_rfwrite_locked(struct zd_chip *chip, u32 value, u8 bits) { … } int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value); int zd_rfwritev_locked(struct zd_chip *chip, const u32* values, unsigned int count, u8 bits); int zd_rfwritev_cr_locked(struct zd_chip *chip, const u32* values, unsigned int count); /* Locking functions for reading and writing registers. * The different parameters are intentional. */ int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value); int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value); int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value); int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value); int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, u32 *values, unsigned int count); int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, unsigned int count); int zd_chip_set_channel(struct zd_chip *chip, u8 channel); static inline u8 _zd_chip_get_channel(struct zd_chip *chip) { … } u8 zd_chip_get_channel(struct zd_chip *chip); int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain); int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr); int zd_write_bssid(struct zd_chip *chip, const u8 *bssid); int zd_chip_switch_radio_on(struct zd_chip *chip); int zd_chip_switch_radio_off(struct zd_chip *chip); int zd_chip_enable_int(struct zd_chip *chip); void zd_chip_disable_int(struct zd_chip *chip); int zd_chip_enable_rxtx(struct zd_chip *chip); void zd_chip_disable_rxtx(struct zd_chip *chip); int zd_chip_enable_hwint(struct zd_chip *chip); int zd_chip_disable_hwint(struct zd_chip *chip); int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel); int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, int preamble); static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type) { … } static inline int zd_set_encryption_type(struct zd_chip *chip, u32 type) { … } static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates) { … } int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates); int zd_chip_lock_phy_regs(struct zd_chip *chip); int zd_chip_unlock_phy_regs(struct zd_chip *chip); enum led_status { … }; int zd_chip_control_leds(struct zd_chip *chip, enum led_status status); int zd_set_beacon_interval(struct zd_chip *chip, u16 interval, u8 dtim_period, int type); static inline int zd_get_beacon_interval(struct zd_chip *chip, u32 *interval) { … } struct rx_status; u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status); struct zd_mc_hash { … }; static inline void zd_mc_clear(struct zd_mc_hash *hash) { … } static inline void zd_mc_add_all(struct zd_mc_hash *hash) { … } static inline void zd_mc_add_addr(struct zd_mc_hash *hash, u8 *addr) { … } int zd_chip_set_multicast_hash(struct zd_chip *chip, struct zd_mc_hash *hash); u64 zd_chip_get_tsf(struct zd_chip *chip); #endif /* _ZD_CHIP_H */
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