linux/drivers/net/ieee802154/mrf24j40.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
 *
 * Copyright (C) 2012 Alan Ott <[email protected]>
 *                    Signal 11 Software
 */

#include <linux/spi/spi.h>
#include <linux/interrupt.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/ieee802154.h>
#include <linux/irq.h>
#include <net/cfg802154.h>
#include <net/mac802154.h>

/* MRF24J40 Short Address Registers */
#define REG_RXMCR
#define BIT_PROMI
#define BIT_ERRPKT
#define BIT_NOACKRSP
#define BIT_PANCOORD

#define REG_PANIDL
#define REG_PANIDH
#define REG_SADRL
#define REG_SADRH
#define REG_EADR0
#define REG_EADR1
#define REG_EADR2
#define REG_EADR3
#define REG_EADR4
#define REG_EADR5
#define REG_EADR6
#define REG_EADR7
#define REG_RXFLUSH
#define REG_ORDER
#define REG_TXMCR
#define TXMCR_MIN_BE_SHIFT
#define TXMCR_MIN_BE_MASK
#define TXMCR_CSMA_RETRIES_SHIFT
#define TXMCR_CSMA_RETRIES_MASK

#define REG_ACKTMOUT
#define REG_ESLOTG1
#define REG_SYMTICKL
#define REG_SYMTICKH
#define REG_PACON0
#define REG_PACON1
#define REG_PACON2
#define REG_TXBCON0
#define REG_TXNCON
#define BIT_TXNTRIG
#define BIT_TXNSECEN
#define BIT_TXNACKREQ

#define REG_TXG1CON
#define REG_TXG2CON
#define REG_ESLOTG23
#define REG_ESLOTG45
#define REG_ESLOTG67
#define REG_TXPEND
#define REG_WAKECON
#define REG_FROMOFFSET
#define REG_TXSTAT
#define REG_TXBCON1
#define REG_GATECLK
#define REG_TXTIME
#define REG_HSYMTMRL
#define REG_HSYMTMRH
#define REG_SOFTRST
#define REG_SECCON0
#define REG_SECCON1
#define REG_TXSTBL
#define REG_RXSR
#define REG_INTSTAT
#define BIT_TXNIF
#define BIT_RXIF
#define BIT_SECIF
#define BIT_SECIGNORE

#define REG_INTCON
#define BIT_TXNIE
#define BIT_RXIE
#define BIT_SECIE

#define REG_GPIO
#define REG_TRISGPIO
#define REG_SLPACK
#define REG_RFCTL
#define BIT_RFRST

#define REG_SECCR2
#define REG_BBREG0
#define REG_BBREG1
#define BIT_RXDECINV

#define REG_BBREG2
#define BBREG2_CCA_MODE_SHIFT
#define BBREG2_CCA_MODE_MASK

#define REG_BBREG3
#define REG_BBREG4
#define REG_BBREG6
#define REG_CCAEDTH

/* MRF24J40 Long Address Registers */
#define REG_RFCON0
#define RFCON0_CH_SHIFT
#define RFCON0_CH_MASK
#define RFOPT_RECOMMEND

#define REG_RFCON1
#define REG_RFCON2
#define REG_RFCON3

#define TXPWRL_MASK
#define TXPWRL_SHIFT
#define TXPWRL_30
#define TXPWRL_20
#define TXPWRL_10
#define TXPWRL_0

#define TXPWRS_MASK
#define TXPWRS_SHIFT
#define TXPWRS_6_3
#define TXPWRS_4_9
#define TXPWRS_3_7
#define TXPWRS_2_8
#define TXPWRS_1_9
#define TXPWRS_1_2
#define TXPWRS_0_5
#define TXPWRS_0

#define REG_RFCON5
#define REG_RFCON6
#define REG_RFCON7
#define REG_RFCON8
#define REG_SLPCAL0
#define REG_SLPCAL1
#define REG_SLPCAL2
#define REG_RFSTATE
#define REG_RSSI
#define REG_SLPCON0
#define BIT_INTEDGE

#define REG_SLPCON1
#define REG_WAKETIMEL
#define REG_WAKETIMEH
#define REG_REMCNTL
#define REG_REMCNTH
#define REG_MAINCNT0
#define REG_MAINCNT1
#define REG_MAINCNT2
#define REG_MAINCNT3
#define REG_TESTMODE
#define REG_ASSOEAR0
#define REG_ASSOEAR1
#define REG_ASSOEAR2
#define REG_ASSOEAR3
#define REG_ASSOEAR4
#define REG_ASSOEAR5
#define REG_ASSOEAR6
#define REG_ASSOEAR7
#define REG_ASSOSAR0
#define REG_ASSOSAR1
#define REG_UNONCE0
#define REG_UNONCE1
#define REG_UNONCE2
#define REG_UNONCE3
#define REG_UNONCE4
#define REG_UNONCE5
#define REG_UNONCE6
#define REG_UNONCE7
#define REG_UNONCE8
#define REG_UNONCE9
#define REG_UNONCE10
#define REG_UNONCE11
#define REG_UNONCE12
#define REG_RX_FIFO

/* Device configuration: Only channels 11-26 on page 0 are supported. */
#define MRF24J40_CHAN_MIN
#define MRF24J40_CHAN_MAX
#define CHANNEL_MASK

#define TX_FIFO_SIZE
#define RX_FIFO_SIZE
#define SET_CHANNEL_DELAY_US

enum mrf24j40_modules {};

/* Device Private Data */
struct mrf24j40 {};

/* regmap information for short address register access */
#define MRF24J40_SHORT_WRITE
#define MRF24J40_SHORT_READ
#define MRF24J40_SHORT_NUMREGS

/* regmap information for long address register access */
#define MRF24J40_LONG_ACCESS
#define MRF24J40_LONG_NUMREGS

/* Read/Write SPI Commands for Short and Long Address registers. */
#define MRF24J40_READSHORT(reg)
#define MRF24J40_WRITESHORT(reg)
#define MRF24J40_READLONG(reg)
#define MRF24J40_WRITELONG(reg)

/* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
#define MAX_SPI_SPEED_HZ

#define printdev(X)

static bool
mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
{}

static bool
mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)
{}

static bool
mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)
{}

static bool
mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)
{}

static const struct regmap_config mrf24j40_short_regmap =;

static bool
mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)
{}

static bool
mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)
{}

static bool
mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)
{}

static const struct regmap_config mrf24j40_long_regmap =;

static int mrf24j40_long_regmap_write(void *context, const void *data,
				      size_t count)
{}

static int
mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,
			  void *val, size_t val_size)
{}

static const struct regmap_bus mrf24j40_long_regmap_bus =;

static void write_tx_buf_complete(void *context)
{}

/* This function relies on an undocumented write method. Once a write command
   and address is set, as many bytes of data as desired can be clocked into
   the device. The datasheet only shows setting one byte at a time. */
static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
			const u8 *data, size_t length)
{}

static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
{}

static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
{}

static int mrf24j40_start(struct ieee802154_hw *hw)
{}

static void mrf24j40_stop(struct ieee802154_hw *hw)
{}

static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
{}

static int mrf24j40_filter(struct ieee802154_hw *hw,
			   struct ieee802154_hw_addr_filt *filt,
			   unsigned long changed)
{}

static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
{}

static void mrf24j40_handle_rx_read_buf_complete(void *context)
{}

static void mrf24j40_handle_rx_read_buf(void *context)
{}

static void mrf24j40_handle_rx_read_len(void *context)
{}

static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
{}

static int
mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
		     u8 retries)
{}

static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
				 const struct wpan_phy_cca *cca)
{}

/* array for representing ed levels */
static const s32 mrf24j40_ed_levels[] =;

/* map ed levels to register value */
static const s32 mrf24j40_ed_levels_map[][2] =;

static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
{}

static const s32 mrf24j40ma_powers[] =;

static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm)
{}

static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
{}

static const struct ieee802154_ops mrf24j40_ops =;

static void mrf24j40_intstat_complete(void *context)
{}

static irqreturn_t mrf24j40_isr(int irq, void *data)
{}

static int mrf24j40_hw_init(struct mrf24j40 *devrec)
{}

static void
mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
{}

static void
mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
{}

static void
mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)
{}

static void  mrf24j40_phy_setup(struct mrf24j40 *devrec)
{}

static int mrf24j40_probe(struct spi_device *spi)
{}

static void mrf24j40_remove(struct spi_device *spi)
{}

static const struct of_device_id mrf24j40_of_match[] =;
MODULE_DEVICE_TABLE(of, mrf24j40_of_match);

static const struct spi_device_id mrf24j40_ids[] =;
MODULE_DEVICE_TABLE(spi, mrf24j40_ids);

static struct spi_driver mrf24j40_driver =;

module_spi_driver();

MODULE_LICENSE();
MODULE_AUTHOR();
MODULE_DESCRIPTION();