/* CoreChip-sz SR9800 one chip USB 2.0 Ethernet Devices * * Author : Liu Junliang <[email protected]> * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #ifndef _SR9800_H #define _SR9800_H /* SR9800 spec. command table on Linux Platform */ /* command : Software Station Management Control Reg */ #define SR_CMD_SET_SW_MII … /* command : PHY Read Reg */ #define SR_CMD_READ_MII_REG … /* command : PHY Write Reg */ #define SR_CMD_WRITE_MII_REG … /* command : Hardware Station Management Control Reg */ #define SR_CMD_SET_HW_MII … /* command : SROM Read Reg */ #define SR_CMD_READ_EEPROM … /* command : SROM Write Reg */ #define SR_CMD_WRITE_EEPROM … /* command : SROM Write Enable Reg */ #define SR_CMD_WRITE_ENABLE … /* command : SROM Write Disable Reg */ #define SR_CMD_WRITE_DISABLE … /* command : RX Control Read Reg */ #define SR_CMD_READ_RX_CTL … #define SR_RX_CTL_PRO … #define SR_RX_CTL_AMALL … #define SR_RX_CTL_SEP … #define SR_RX_CTL_AB … #define SR_RX_CTL_AM … #define SR_RX_CTL_AP … #define SR_RX_CTL_ARP … #define SR_RX_CTL_SO … #define SR_RX_CTL_RH1M … #define SR_RX_CTL_RH2M … #define SR_RX_CTL_RH3M … /* command : RX Control Write Reg */ #define SR_CMD_WRITE_RX_CTL … /* command : IPG0/IPG1/IPG2 Control Read Reg */ #define SR_CMD_READ_IPG012 … /* command : IPG0/IPG1/IPG2 Control Write Reg */ #define SR_CMD_WRITE_IPG012 … /* command : Node ID Read Reg */ #define SR_CMD_READ_NODE_ID … /* command : Node ID Write Reg */ #define SR_CMD_WRITE_NODE_ID … /* command : Multicast Filter Array Read Reg */ #define SR_CMD_READ_MULTI_FILTER … /* command : Multicast Filter Array Write Reg */ #define SR_CMD_WRITE_MULTI_FILTER … /* command : Eth/HomePNA PHY Address Reg */ #define SR_CMD_READ_PHY_ID … /* command : Medium Status Read Reg */ #define SR_CMD_READ_MEDIUM_STATUS … #define SR_MONITOR_LINK … #define SR_MONITOR_MAGIC … #define SR_MONITOR_HSFS … /* command : Medium Status Write Reg */ #define SR_CMD_WRITE_MEDIUM_MODE … #define SR_MEDIUM_GM … #define SR_MEDIUM_FD … #define SR_MEDIUM_AC … #define SR_MEDIUM_ENCK … #define SR_MEDIUM_RFC … #define SR_MEDIUM_TFC … #define SR_MEDIUM_JFE … #define SR_MEDIUM_PF … #define SR_MEDIUM_RE … #define SR_MEDIUM_PS … #define SR_MEDIUM_RSV … #define SR_MEDIUM_SBP … #define SR_MEDIUM_SM … /* command : Monitor Mode Status Read Reg */ #define SR_CMD_READ_MONITOR_MODE … /* command : Monitor Mode Status Write Reg */ #define SR_CMD_WRITE_MONITOR_MODE … /* command : GPIO Status Read Reg */ #define SR_CMD_READ_GPIOS … #define SR_GPIO_GPO0EN … #define SR_GPIO_GPO_0 … #define SR_GPIO_GPO1EN … #define SR_GPIO_GPO_1 … #define SR_GPIO_GPO2EN … #define SR_GPIO_GPO_2 … #define SR_GPIO_RESERVED … #define SR_GPIO_RSE … /* command : GPIO Status Write Reg */ #define SR_CMD_WRITE_GPIOS … /* command : Eth PHY Power and Reset Control Reg */ #define SR_CMD_SW_RESET … #define SR_SWRESET_CLEAR … #define SR_SWRESET_RR … #define SR_SWRESET_RT … #define SR_SWRESET_PRTE … #define SR_SWRESET_PRL … #define SR_SWRESET_BZ … #define SR_SWRESET_IPRL … #define SR_SWRESET_IPPD … /* command : Software Interface Selection Status Read Reg */ #define SR_CMD_SW_PHY_STATUS … /* command : Software Interface Selection Status Write Reg */ #define SR_CMD_SW_PHY_SELECT … /* command : BULK in Buffer Size Reg */ #define SR_CMD_BULKIN_SIZE … /* command : LED_MUX Control Reg */ #define SR_CMD_LED_MUX … #define SR_LED_MUX_TX_ACTIVE … #define SR_LED_MUX_RX_ACTIVE … #define SR_LED_MUX_COLLISION … #define SR_LED_MUX_DUP_COL … #define SR_LED_MUX_DUP … #define SR_LED_MUX_SPEED … #define SR_LED_MUX_LINK_ACTIVE … #define SR_LED_MUX_LINK … /* Register Access Flags */ #define SR_REQ_RD_REG … #define SR_REQ_WR_REG … /* Multicast Filter Array size & Max Number */ #define SR_MCAST_FILTER_SIZE … #define SR_MAX_MCAST … /* IPG0/1/2 Default Value */ #define SR9800_IPG0_DEFAULT … #define SR9800_IPG1_DEFAULT … #define SR9800_IPG2_DEFAULT … /* Medium Status Default Mode */ #define SR9800_MEDIUM_DEFAULT … /* RX Control Default Setting */ #define SR_DEFAULT_RX_CTL … /* EEPROM Magic Number & EEPROM Size */ #define SR_EEPROM_MAGIC … #define SR9800_EEPROM_LEN … /* SR9800 Driver Version and Driver Name */ #define DRIVER_VERSION … #define DRIVER_NAME … #define DRIVER_FLAG … /* SR9800 BULKIN Buffer Size */ #define SR9800_MAX_BULKIN_2K … #define SR9800_MAX_BULKIN_4K … #define SR9800_MAX_BULKIN_6K … #define SR9800_MAX_BULKIN_8K … #define SR9800_MAX_BULKIN_16K … #define SR9800_MAX_BULKIN_20K … #define SR9800_MAX_BULKIN_24K … #define SR9800_MAX_BULKIN_32K … static const struct { … } SR9800_BULKIN_SIZE[] = …; /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ struct sr_data { … }; struct sr9800_int_data { … } __packed; #endif /* _SR9800_H */
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