/* SPDX-License-Identifier: GPL-2.0-or-later */ /*************************************************************************** * * Copyright (C) 2007-2008 SMSC * *****************************************************************************/ #ifndef _SMSC95XX_H #define _SMSC95XX_H /* Tx command words */ #define TX_CMD_A_DATA_OFFSET_ … #define TX_CMD_A_FIRST_SEG_ … #define TX_CMD_A_LAST_SEG_ … #define TX_CMD_A_BUF_SIZE_ … #define TX_CMD_B_CSUM_ENABLE … #define TX_CMD_B_ADD_CRC_DIS_ … #define TX_CMD_B_DIS_PADDING_ … #define TX_CMD_B_FRAME_LENGTH_ … /* Rx status word */ #define RX_STS_FF_ … #define RX_STS_FL_ … #define RX_STS_ES_ … #define RX_STS_BF_ … #define RX_STS_LE_ … #define RX_STS_RF_ … #define RX_STS_MF_ … #define RX_STS_TL_ … #define RX_STS_CS_ … #define RX_STS_FT_ … #define RX_STS_RW_ … #define RX_STS_ME_ … #define RX_STS_DB_ … #define RX_STS_CRC_ … /* SCSRs - System Control and Status Registers */ /* Device ID and Revision Register */ #define ID_REV … #define ID_REV_CHIP_ID_MASK_ … #define ID_REV_CHIP_REV_MASK_ … #define ID_REV_CHIP_ID_9500_ … #define ID_REV_CHIP_ID_9500A_ … #define ID_REV_CHIP_ID_9512_ … #define ID_REV_CHIP_ID_9530_ … #define ID_REV_CHIP_ID_89530_ … #define ID_REV_CHIP_ID_9730_ … /* Interrupt Status Register */ #define INT_STS … #define INT_STS_MAC_RTO_ … #define INT_STS_TX_STOP_ … #define INT_STS_RX_STOP_ … #define INT_STS_PHY_INT_ … #define INT_STS_TXE_ … #define INT_STS_TDFU_ … #define INT_STS_TDFO_ … #define INT_STS_RXDF_ … #define INT_STS_GPIOS_ … #define INT_STS_CLEAR_ALL_ … /* Receive Configuration Register */ #define RX_CFG … #define RX_FIFO_FLUSH_ … /* Transmit Configuration Register */ #define TX_CFG … #define TX_CFG_ON_ … #define TX_CFG_STOP_ … #define TX_CFG_FIFO_FLUSH_ … /* Hardware Configuration Register */ #define HW_CFG … #define HW_CFG_BIR_ … #define HW_CFG_LEDB_ … #define HW_CFG_RXDOFF_ … #define HW_CFG_SBP_ … #define HW_CFG_IME_ … #define HW_CFG_DRP_ … #define HW_CFG_MEF_ … #define HW_CFG_ETC_ … #define HW_CFG_LRST_ … #define HW_CFG_PSEL_ … #define HW_CFG_BCE_ … #define HW_CFG_SRST_ … /* Receive FIFO Information Register */ #define RX_FIFO_INF … #define RX_FIFO_INF_USED_ … /* Transmit FIFO Information Register */ #define TX_FIFO_INF … #define TX_FIFO_INF_FREE_ … /* Power Management Control Register */ #define PM_CTRL … #define PM_CTL_RES_CLR_WKP_STS … #define PM_CTL_RES_CLR_WKP_EN … #define PM_CTL_DEV_RDY_ … #define PM_CTL_SUS_MODE_ … #define PM_CTL_SUS_MODE_0 … #define PM_CTL_SUS_MODE_1 … #define PM_CTL_SUS_MODE_2 … #define PM_CTL_SUS_MODE_3 … #define PM_CTL_PHY_RST_ … #define PM_CTL_WOL_EN_ … #define PM_CTL_ED_EN_ … #define PM_CTL_WUPS_ … #define PM_CTL_WUPS_NO_ … #define PM_CTL_WUPS_ED_ … #define PM_CTL_WUPS_WOL_ … #define PM_CTL_WUPS_MULTI_ … /* LED General Purpose IO Configuration Register */ #define LED_GPIO_CFG … #define LED_GPIO_CFG_SPD_LED … #define LED_GPIO_CFG_LNK_LED … #define LED_GPIO_CFG_FDX_LED … /* General Purpose IO Configuration Register */ #define GPIO_CFG … /* Automatic Flow Control Configuration Register */ #define AFC_CFG … #define AFC_CFG_HI_ … #define AFC_CFG_LO_ … #define AFC_CFG_BACK_DUR_ … #define AFC_CFG_FC_MULT_ … #define AFC_CFG_FC_BRD_ … #define AFC_CFG_FC_ADD_ … #define AFC_CFG_FC_ANY_ … /* Hi watermark = 15.5Kb (~10 mtu pkts) */ /* low watermark = 3k (~2 mtu pkts) */ /* backpressure duration = ~ 350us */ /* Apply FC on any frame. */ #define AFC_CFG_DEFAULT … /* EEPROM Command Register */ #define E2P_CMD … #define E2P_CMD_BUSY_ … #define E2P_CMD_MASK_ … #define E2P_CMD_READ_ … #define E2P_CMD_EWDS_ … #define E2P_CMD_EWEN_ … #define E2P_CMD_WRITE_ … #define E2P_CMD_WRAL_ … #define E2P_CMD_ERASE_ … #define E2P_CMD_ERAL_ … #define E2P_CMD_RELOAD_ … #define E2P_CMD_TIMEOUT_ … #define E2P_CMD_LOADED_ … #define E2P_CMD_ADDR_ … #define MAX_EEPROM_SIZE … /* EEPROM Data Register */ #define E2P_DATA … #define E2P_DATA_MASK_ … /* Burst Cap Register */ #define BURST_CAP … #define BURST_CAP_MASK_ … /* Configuration Straps Status Register */ #define STRAP_STATUS … #define STRAP_STATUS_PWR_SEL_ … #define STRAP_STATUS_AMDIX_EN_ … #define STRAP_STATUS_PORT_SWAP_ … #define STRAP_STATUS_EEP_SIZE_ … #define STRAP_STATUS_RMT_WKP_ … #define STRAP_STATUS_EEP_DISABLE_ … /* Data Port Select Register */ #define DP_SEL … /* Data Port Command Register */ #define DP_CMD … /* Data Port Address Register */ #define DP_ADDR … /* Data Port Data 0 Register */ #define DP_DATA0 … /* Data Port Data 1 Register */ #define DP_DATA1 … /* General Purpose IO Wake Enable and Polarity Register */ #define GPIO_WAKE … /* Interrupt Endpoint Control Register */ #define INT_EP_CTL … #define INT_EP_CTL_INTEP_ … #define INT_EP_CTL_MAC_RTO_ … #define INT_EP_CTL_RX_FIFO_ … #define INT_EP_CTL_TX_STOP_ … #define INT_EP_CTL_RX_STOP_ … #define INT_EP_CTL_PHY_INT_ … #define INT_EP_CTL_TXE_ … #define INT_EP_CTL_TDFU_ … #define INT_EP_CTL_TDFO_ … #define INT_EP_CTL_RXDF_ … #define INT_EP_CTL_GPIOS_ … /* Bulk In Delay Register (units of 16.667ns, until ~1092µs) */ #define BULK_IN_DLY … /* MAC CSRs - MAC Control and Status Registers */ /* MAC Control Register */ #define MAC_CR … #define MAC_CR_RXALL_ … #define MAC_CR_RCVOWN_ … #define MAC_CR_LOOPBK_ … #define MAC_CR_FDPX_ … #define MAC_CR_MCPAS_ … #define MAC_CR_PRMS_ … #define MAC_CR_INVFILT_ … #define MAC_CR_PASSBAD_ … #define MAC_CR_HFILT_ … #define MAC_CR_HPFILT_ … #define MAC_CR_LCOLL_ … #define MAC_CR_BCAST_ … #define MAC_CR_DISRTY_ … #define MAC_CR_PADSTR_ … #define MAC_CR_BOLMT_MASK … #define MAC_CR_DFCHK_ … #define MAC_CR_TXEN_ … #define MAC_CR_RXEN_ … /* MAC Address High Register */ #define ADDRH … /* MAC Address Low Register */ #define ADDRL … /* Multicast Hash Table High Register */ #define HASHH … /* Multicast Hash Table Low Register */ #define HASHL … /* MII Access Register */ #define MII_ADDR … #define MII_WRITE_ … #define MII_BUSY_ … #define MII_READ_ … /* MII Data Register */ #define MII_DATA … /* Flow Control Register */ #define FLOW … #define FLOW_FCPT_ … #define FLOW_FCPASS_ … #define FLOW_FCEN_ … #define FLOW_FCBSY_ … /* VLAN1 Tag Register */ #define VLAN1 … /* VLAN2 Tag Register */ #define VLAN2 … /* Wake Up Frame Filter Register */ #define WUFF … #define LAN9500_WUFF_NUM … #define LAN9500A_WUFF_NUM … /* Wake Up Control and Status Register */ #define WUCSR … #define WUCSR_WFF_PTR_RST_ … #define WUCSR_GUE_ … #define WUCSR_WUFR_ … #define WUCSR_MPR_ … #define WUCSR_WAKE_EN_ … #define WUCSR_MPEN_ … /* Checksum Offload Engine Control Register */ #define COE_CR … #define Tx_COE_EN_ … #define Rx_COE_MODE_ … #define Rx_COE_EN_ … /* Vendor-specific PHY Definitions (via MII access) */ /* EDPD NLP / crossover time configuration (LAN9500A only) */ #define PHY_EDPD_CONFIG … #define PHY_EDPD_CONFIG_TX_NLP_EN_ … #define PHY_EDPD_CONFIG_TX_NLP_1000_ … #define PHY_EDPD_CONFIG_TX_NLP_768_ … #define PHY_EDPD_CONFIG_TX_NLP_512_ … #define PHY_EDPD_CONFIG_TX_NLP_256_ … #define PHY_EDPD_CONFIG_RX_1_NLP_ … #define PHY_EDPD_CONFIG_RX_NLP_64_ … #define PHY_EDPD_CONFIG_RX_NLP_256_ … #define PHY_EDPD_CONFIG_RX_NLP_512_ … #define PHY_EDPD_CONFIG_RX_NLP_1000_ … #define PHY_EDPD_CONFIG_EXT_CROSSOVER_ … #define PHY_EDPD_CONFIG_DEFAULT … /* Mode Control/Status Register */ #define PHY_MODE_CTRL_STS … #define MODE_CTRL_STS_EDPWRDOWN_ … #define MODE_CTRL_STS_ENERGYON_ … /* Control/Status Indication Register */ #define SPECIAL_CTRL_STS … #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ … #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ … #define SPECIAL_CTRL_STS_AMDIX_STATE_ … /* Interrupt Source Register */ #define PHY_INT_SRC … #define PHY_INT_SRC_ENERGY_ON_ … #define PHY_INT_SRC_ANEG_COMP_ … #define PHY_INT_SRC_REMOTE_FAULT_ … #define PHY_INT_SRC_LINK_DOWN_ … /* Interrupt Mask Register */ #define PHY_INT_MASK … #define PHY_INT_MASK_ENERGY_ON_ … #define PHY_INT_MASK_ANEG_COMP_ … #define PHY_INT_MASK_REMOTE_FAULT_ … #define PHY_INT_MASK_LINK_DOWN_ … #define PHY_INT_MASK_DEFAULT_ … /* PHY Special Control/Status Register */ #define PHY_SPECIAL … #define PHY_SPECIAL_SPD_ … #define PHY_SPECIAL_SPD_10HALF_ … #define PHY_SPECIAL_SPD_10FULL_ … #define PHY_SPECIAL_SPD_100HALF_ … #define PHY_SPECIAL_SPD_100FULL_ … /* USB Vendor Requests */ #define USB_VENDOR_REQUEST_WRITE_REGISTER … #define USB_VENDOR_REQUEST_READ_REGISTER … #define USB_VENDOR_REQUEST_GET_STATS … /* Interrupt Endpoint status word bitfields */ #define INT_ENP_MAC_RTO_ … #define INT_ENP_TX_STOP_ … #define INT_ENP_RX_STOP_ … #define INT_ENP_PHY_INT_ … #define INT_ENP_TXE_ … #define INT_ENP_TDFU_ … #define INT_ENP_TDFO_ … #define INT_ENP_RXDF_ … #endif /* _SMSC95XX_H */
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