linux/drivers/video/fbdev/kyro/STG4000InitDevice.c

/*
 *  linux/drivers/video/kyro/STG4000InitDevice.c
 *
 *  Copyright (C) 2000 Imagination Technologies Ltd
 *  Copyright (C) 2002 STMicroelectronics
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/pci.h>

#include "STG4000Reg.h"
#include "STG4000Interface.h"

/* SDRAM fixed settings */
#define SDRAM_CFG_0 …
#define SDRAM_CFG_1 …
#define SDRAM_CFG_2 …
#define SDRAM_ARB_CFG …
#define SDRAM_REFRESH …

/* Reset values */
#define PMX2_SOFTRESET_DAC_RST …
#define PMX2_SOFTRESET_C1_RST …
#define PMX2_SOFTRESET_C2_RST …
#define PMX2_SOFTRESET_3D_RST …
#define PMX2_SOFTRESET_VIDIN_RST …
#define PMX2_SOFTRESET_TLB_RST …
#define PMX2_SOFTRESET_SD_RST …
#define PMX2_SOFTRESET_VGA_RST …
#define PMX2_SOFTRESET_ROM_RST …
#define PMX2_SOFTRESET_TA_RST …
#define PMX2_SOFTRESET_REG_RST …
#define PMX2_SOFTRESET_ALL …

/* Core clock freq */
#define CORE_PLL_FREQ …

/* Reference Clock freq */
#define REF_FREQ …

/* PCI Registers */
static u16 CorePllControl = …;

#define PCI_CONFIG_SUBSYS_ID …

/* Misc */
#define CORE_PLL_MODE_REG_0_7 …
#define CORE_PLL_MODE_REG_8_15 …
#define CORE_PLL_MODE_CONFIG_REG …
#define DAC_PLL_CONFIG_REG …

#define STG_MAX_VCO …
#define STG_MIN_VCO …

/* PLL Clock */
#define STG4K3_PLL_SCALER …
#define STG4K3_PLL_MIN_R …
#define STG4K3_PLL_MAX_R …
#define STG4K3_PLL_MIN_F …
#define STG4K3_PLL_MAX_F …
#define STG4K3_PLL_MIN_OD …
#define STG4K3_PLL_MAX_OD …
#define STG4K3_PLL_MIN_VCO_SC …
#define STG4K3_PLL_MAX_VCO_SC …
#define STG4K3_PLL_MINR_VCO_SC …
#define STG4K3_PLL_MAXR_VCO_SC …
#define STG4K3_PLL_MINR_VCO …
#define STG4K3_PLL_MAX_VCO …
#define STG4K3_PLL_MAXR_VCO …

#define OS_DELAY(X) …

static u32 InitSDRAMRegisters(volatile STG4000REG __iomem *pSTGReg,
			      u32 dwSubSysID, u32 dwRevID)
{ … }

u32 ProgramClock(u32 refClock,
		   u32 coreClock,
		   u32 * FOut, u32 * ROut, u32 * POut)
{ … }

int SetCoreClockPLL(volatile STG4000REG __iomem *pSTGReg, struct pci_dev *pDev)
{ … }