/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2008 Andres Salomon <[email protected]> * * Geode GX2 header information */ #ifndef _GXFB_H_ #define _GXFB_H_ #include <linux/io.h> #define GP_REG_COUNT … #define DC_REG_COUNT … #define VP_REG_COUNT … #define FP_REG_COUNT … #define DC_PAL_COUNT … struct gxfb_par { … }; unsigned int gx_frame_buffer_size(void); int gx_line_delta(int xres, int bpp); void gx_set_mode(struct fb_info *info); void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno, unsigned red, unsigned green, unsigned blue); void gx_set_dclk_frequency(struct fb_info *info); void gx_configure_display(struct fb_info *info); int gx_blank_display(struct fb_info *info, int blank_mode); int gx_powerdown(struct fb_info *info); int gx_powerup(struct fb_info *info); /* Graphics Processor registers (table 6-23 from the data book) */ enum gp_registers { … }; #define GP_BLT_STATUS_BLT_PENDING … #define GP_BLT_STATUS_BLT_BUSY … /* Display Controller registers (table 6-38 from the data book) */ enum dc_registers { … }; #define DC_UNLOCK_LOCK … #define DC_UNLOCK_UNLOCK … #define DC_GENERAL_CFG_YUVM … #define DC_GENERAL_CFG_VDSE … #define DC_GENERAL_CFG_DFHPEL_SHIFT … #define DC_GENERAL_CFG_DFHPSL_SHIFT … #define DC_GENERAL_CFG_DECE … #define DC_GENERAL_CFG_CMPE … #define DC_GENERAL_CFG_VIDE … #define DC_GENERAL_CFG_ICNE … #define DC_GENERAL_CFG_CURE … #define DC_GENERAL_CFG_DFLE … #define DC_DISPLAY_CFG_A20M … #define DC_DISPLAY_CFG_A18M … #define DC_DISPLAY_CFG_PALB … #define DC_DISPLAY_CFG_DISP_MODE_24BPP … #define DC_DISPLAY_CFG_DISP_MODE_16BPP … #define DC_DISPLAY_CFG_DISP_MODE_8BPP … #define DC_DISPLAY_CFG_VDEN … #define DC_DISPLAY_CFG_GDEN … #define DC_DISPLAY_CFG_TGEN … /* * Video Processor registers (table 6-54). * There is space for 64 bit values, but we never use more than the * lower 32 bits. The actual register save/restore code only bothers * to restore those 32 bits. */ enum vp_registers { … }; #define VP_VCFG_VID_EN … #define VP_DCFG_DAC_VREF … #define VP_DCFG_GV_GAM … #define VP_DCFG_VG_CK … #define VP_DCFG_CRT_SYNC_SKW_DEFAULT … #define VP_DCFG_CRT_SYNC_SKW … #define VP_DCFG_CRT_VSYNC_POL … #define VP_DCFG_CRT_HSYNC_POL … #define VP_DCFG_FP_DATA_EN … #define VP_DCFG_FP_PWR_EN … #define VP_DCFG_DAC_BL_EN … #define VP_DCFG_VSYNC_EN … #define VP_DCFG_HSYNC_EN … #define VP_DCFG_CRT_EN … #define VP_MISC_GAM_EN … #define VP_MISC_DACPWRDN … #define VP_MISC_APWRDN … /* * Flat Panel registers (table 6-55). * Also 64 bit registers; see above note about 32-bit handling. */ /* we're actually in the VP register space, starting at address 0x400 */ #define VP_FP_START … enum fp_registers { … }; #define FP_PT1_VSIZE_SHIFT … #define FP_PT1_VSIZE_MASK … #define FP_PT2_HSP … #define FP_PT2_VSP … #define FP_PM_P … #define FP_PM_PANEL_PWR_UP … #define FP_PM_PANEL_PWR_DOWN … #define FP_PM_PANEL_OFF … #define FP_PM_PANEL_ON … #define FP_DFC_NFI … /* register access functions */ static inline uint32_t read_gp(struct gxfb_par *par, int reg) { … } static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val) { … } static inline uint32_t read_dc(struct gxfb_par *par, int reg) { … } static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val) { … } static inline uint32_t read_vp(struct gxfb_par *par, int reg) { … } static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val) { … } static inline uint32_t read_fp(struct gxfb_par *par, int reg) { … } static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val) { … } /* MSRs are defined in linux/cs5535.h; their bitfields are here */ #define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 … #define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 … #define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 … #define MSR_GLCP_DOTPLL_LOCK … #define MSR_GLCP_DOTPLL_BYPASS … #define MSR_GLCP_DOTPLL_DOTRESET … #define MSR_GX_MSR_PADSEL_MASK … #define MSR_GX_MSR_PADSEL_TFT … #define MSR_GX_GLD_MSR_CONFIG_FP … #endif
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