/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _FORE200E_H #define _FORE200E_H #ifdef __KERNEL__ /* rx buffer sizes */ #define SMALL_BUFFER_SIZE … #define LARGE_BUFFER_SIZE … #define RBD_BLK_SIZE … #define MAX_PDU_SIZE … #define BUFFER_S1_SIZE … #define BUFFER_L1_SIZE … #define BUFFER_S2_SIZE … #define BUFFER_L2_SIZE … #define BUFFER_S1_NBR … #define BUFFER_L1_NBR … #define BUFFER_S2_NBR … #define BUFFER_L2_NBR … #define QUEUE_SIZE_CMD … #define QUEUE_SIZE_RX … #define QUEUE_SIZE_TX … #define QUEUE_SIZE_BS … #define FORE200E_VPI_BITS … #define FORE200E_VCI_BITS … #define NBR_CONNECT … #define TSD_FIXED … #define TSD_EXTENSION … #define TSD_NBR … /* the cp starts putting a received PDU into one *small* buffer, then it uses a number of *large* buffers for the trailing data. we compute here the total number of receive segment descriptors required to hold the largest possible PDU */ #define RSD_REQUIRED … #define RSD_FIXED … /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU, but we have to keep the size of the receive PDU descriptor multiple of 32 bytes, so we add one extra RSD to RSD_EXTENSION (WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */ #define RSD_EXTENSION … #define RSD_NBR … #define FORE200E_DEV(d) … #define FORE200E_VCC(d) … /* bitfields endian games */ #if defined(__LITTLE_ENDIAN_BITFIELD) #define BITFIELD2(b1, b2) … #define BITFIELD3(b1, b2, b3) … #define BITFIELD4(b1, b2, b3, b4) … #define BITFIELD5(b1, b2, b3, b4, b5) … #define BITFIELD6(b1, b2, b3, b4, b5, b6) … #elif defined(__BIG_ENDIAN_BITFIELD) #define BITFIELD2 … #define BITFIELD3 … #define BITFIELD4 … #define BITFIELD5 … #define BITFIELD6 … #else #error unknown bitfield endianess #endif /* ATM cell header (minus HEC byte) */ atm_header_t; /* ATM adaptation layer id */ fore200e_aal_t; /* transmit PDU descriptor specification */ tpd_spec_t; /* transmit PDU rate control */ tpd_rate_t; /* transmit segment descriptor */ tsd_t; /* transmit PDU descriptor */ tpd_t; /* receive segment descriptor */ rsd_t; /* receive PDU descriptor */ rpd_t; /* buffer scheme */ buffer_scheme_t; /* buffer magnitude */ buffer_magn_t; /* receive buffer descriptor */ rbd_t; /* receive buffer descriptor block */ rbd_block_t; /* tpd DMA address */ tpd_haddr_t; #define TPD_HADDR_SHIFT … /* cp resident transmit queue entry */ cp_txq_entry_t; /* cp resident receive queue entry */ cp_rxq_entry_t; /* cp resident buffer supply queue entry */ cp_bsq_entry_t; /* completion status */ status_t; /* cp operation code */ opcode_t; /* virtual path / virtual channel identifiers */ vpvc_t; /* activate VC command opcode */ activate_opcode_t; /* activate VC command block */ activate_block_t; /* deactivate VC command opcode */ deactivate_opcode_t; /* deactivate VC command block */ deactivate_block_t; /* OC-3 registers */ oc3_regs_t; /* set/get OC-3 regs command opcode */ oc3_opcode_t; /* set/get OC-3 regs command block */ oc3_block_t; /* physical encoding statistics */ stats_phy_t; /* OC-3 statistics */ stats_oc3_t; /* ATM statistics */ stats_atm_t; /* AAL0 statistics */ stats_aal0_t; /* AAL3/4 statistics */ stats_aal34_t; /* AAL5 statistics */ stats_aal5_t; /* auxiliary statistics */ stats_aux_t; /* whole statistics buffer */ stats_t; /* get statistics command opcode */ stats_opcode_t; /* get statistics command block */ stats_block_t; /* expansion PROM data (PCI specific) */ prom_data_t; /* get expansion PROM data command opcode */ prom_opcode_t; /* get expansion PROM data command block */ prom_block_t; /* cp command */ cmd_t; /* cp resident command queue */ cp_cmdq_entry_t; /* host resident transmit queue entry */ host_txq_entry_t; /* host resident receive queue entry */ host_rxq_entry_t; /* host resident buffer supply queue entry */ host_bsq_entry_t; /* host resident command queue entry */ host_cmdq_entry_t; /* chunk of memory */ chunk_t; #define dma_size … /* host resident receive buffer */ buffer_t; #if (BITS_PER_LONG == 32) #define FORE200E_BUF2HDL … #define FORE200E_HDL2BUF … #else /* deal with 64 bit pointers */ #define FORE200E_BUF2HDL(buffer) … #define FORE200E_HDL2BUF(handle) … #endif /* host resident command queue */ host_cmdq_t; /* host resident transmit queue */ host_txq_t; /* host resident receive queue */ host_rxq_t; /* host resident buffer supply queues */ host_bsq_t; /* header of the firmware image */ fw_header_t; #define FW_HEADER_MAGIC … /* receive buffer supply queues scheme specification */ bs_spec_t; /* initialization command block (one-time command, not in cmd queue) */ init_block_t; media_type_t; #define FORE200E_MEDIA_INDEX(media_type) … /* cp resident queues */ cp_queues_t; /* boot status */ boot_status_t; /* software UART */ soft_uart_t; #define FORE200E_CP_MONITOR_UART_FREE … #define FORE200E_CP_MONITOR_UART_AVAIL … /* i960 monitor */ cp_monitor_t; /* device state */ fore200e_state; /* PCA-200E registers */ fore200e_pca_regs_t; /* SBA-200E registers */ fore200e_sba_regs_t; /* model-specific registers */ fore200e_regs; struct fore200e; /* bus-dependent data */ fore200e_bus_t; /* vc mapping */ fore200e_vc_map_t; #define FORE200E_VC_MAP(fore200e, vpi, vci) … /* per-device data */ fore200e_t; /* per-vcc data */ fore200e_vcc_t; /* 200E-series common memory layout */ #define FORE200E_CP_MONITOR_OFFSET … #define FORE200E_CP_QUEUES_OFFSET … /* PCA-200E memory layout */ #define PCA200E_IOSPACE_LENGTH … #define PCA200E_HCR_OFFSET … #define PCA200E_IMR_OFFSET … #define PCA200E_PSR_OFFSET … /* PCA-200E host control register */ #define PCA200E_HCR_RESET … #define PCA200E_HCR_HOLD_LOCK … #define PCA200E_HCR_I960FAIL … #define PCA200E_HCR_INTRB … #define PCA200E_HCR_HOLD_ACK … #define PCA200E_HCR_INTRA … #define PCA200E_HCR_OUTFULL … #define PCA200E_HCR_CLRINTR … #define PCA200E_HCR_ESPHOLD … #define PCA200E_HCR_INFULL … #define PCA200E_HCR_TESTMODE … /* PCA-200E PCI bus interface regs (offsets in PCI config space) */ #define PCA200E_PCI_LATENCY … #define PCA200E_PCI_MASTER_CTRL … #define PCA200E_PCI_THRESHOLD … /* PBI master control register */ #define PCA200E_CTRL_DIS_CACHE_RD … #define PCA200E_CTRL_DIS_WRT_INVAL … #define PCA200E_CTRL_2_CACHE_WRT_INVAL … #define PCA200E_CTRL_IGN_LAT_TIMER … #define PCA200E_CTRL_ENA_CONT_REQ_MODE … #define PCA200E_CTRL_LARGE_PCI_BURSTS … #define PCA200E_CTRL_CONVERT_ENDIAN … #define SBA200E_PROM_NAME … /* size of SBA-200E registers */ #define SBA200E_HCR_LENGTH … #define SBA200E_BSR_LENGTH … #define SBA200E_ISR_LENGTH … #define SBA200E_RAM_LENGTH … /* SBA-200E SBUS burst transfer size register */ #define SBA200E_BSR_BURST4 … #define SBA200E_BSR_BURST8 … #define SBA200E_BSR_BURST16 … /* SBA-200E host control register */ #define SBA200E_HCR_RESET … #define SBA200E_HCR_HOLD_LOCK … #define SBA200E_HCR_I960FAIL … #define SBA200E_HCR_I960SETINTR … #define SBA200E_HCR_OUTFULL … #define SBA200E_HCR_INTR_CLR … #define SBA200E_HCR_INTR_ENA … #define SBA200E_HCR_ESPHOLD … #define SBA200E_HCR_INFULL … #define SBA200E_HCR_TESTMODE … #define SBA200E_HCR_INTR_REQ … #define SBA200E_HCR_STICKY … #endif /* __KERNEL__ */ #endif /* _FORE200E_H */
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