/* SPDX-License-Identifier: GPL-2.0 */ /* drivers/atm/midway.h - Efficient Networks Midway (SAR) description */ /* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */ #ifndef DRIVERS_ATM_MIDWAY_H #define DRIVERS_ATM_MIDWAY_H #define NR_VCI … #define NR_VCI_LD … #define NR_DMA_RX … #define NR_DMA_TX … #define NR_SERVICE … #define NR_CHAN … #define TS_CLOCK … #define MAP_MAX_SIZE … #define EPROM_SIZE … #define MEM_VALID … #define PHY_BASE … #define REG_BASE … #define RAM_BASE … #define RAM_INCREMENT … #define MID_VCI_BASE … #define MID_DMA_RX_BASE … #define MID_DMA_TX_BASE … #define MID_SERVICE_BASE … #define MID_FREE_BASE … #define MAC_LEN … #define MID_MIN_BUF_SIZE … #define MID_MAX_BUF_SIZE … #define RX_DESCR_SIZE … #define TX_DESCR_SIZE … #define AAL5_TRAILER … #define TX_GAP … /* * Midway Reset/ID * * All values read-only. Writing to this register resets Midway chip. */ #define MID_RES_ID_MCON … #define MID_ID … #define MID_SHIFT … #define MID_MOTHER_ID … #define MID_MOTHER_SHIFT … #define MID_CON_TI … #define MID_CON_SUNI … #define MID_CON_V6 … #define DAUGHTER_ID … /* * Interrupt Status Acknowledge, Interrupt Status & Interrupt Enable */ #define MID_ISA … #define MID_IS … #define MID_IE … #define MID_TX_COMPLETE_7 … #define MID_TX_COMPLETE_6 … #define MID_TX_COMPLETE_5 … #define MID_TX_COMPLETE_4 … #define MID_TX_COMPLETE_3 … #define MID_TX_COMPLETE_2 … #define MID_TX_COMPLETE_1 … #define MID_TX_COMPLETE_0 … #define MID_TX_COMPLETE … #define MID_TX_DMA_OVFL … #define MID_TX_IDENT_MISM … #define MID_DMA_LERR_ACK … #define MID_DMA_ERR_ACK … #define MID_RX_DMA_COMPLETE … #define MID_TX_DMA_COMPLETE … #define MID_SERVICE … #define MID_SUNI_INT … #define MID_STAT_OVFL … /* * Master Control/Status */ #define MID_MC_S … #define MID_INT_SELECT … #define MID_INT_SEL_SHIFT … #define MID_TX_LOCK_MODE … #define MID_DMA_ENABLE … #define MID_TX_ENABLE … #define MID_RX_ENABLE … #define MID_WAIT_1MS … #define MID_WAIT_500US … /* * Statistics * * Cleared when reading. */ #define MID_STAT … #define MID_VCI_TRASH … #define MID_VCI_TRASH_SHIFT … #define MID_OVFL_TRASH … /* * Address registers */ #define MID_SERV_WRITE … #define MID_DMA_ADDR … #define MID_DMA_WR_RX … #define MID_DMA_RD_RX … #define MID_DMA_WR_TX … #define MID_DMA_RD_TX … /* * Transmit Place Registers (0x10+4*channel) */ #define MID_TX_PLACE(c) … #define MID_SIZE … #define MID_SIZE_SHIFT … #define MID_LOCATION … #define MID_LOC_SKIP … /* * Transmit ReadPtr Registers (0x11+4*channel) */ #define MID_TX_RDPTR(c) … #define MID_READ_PTR … /* * Transmit DescrStart Registers (0x12+4*channel) */ #define MID_TX_DESCRSTART(c) … #define MID_DESCR_START … #define ENI155_MAGIC … struct midway_eprom { … }; /* * VCI table entry */ #define MID_VCI_IN_SERVICE … #define MID_VCI_SIZE … #define MID_VCI_SIZE_SHIFT … #define MID_VCI_LOCATION … #define MID_VCI_LOCATION_SHIFT … #define MID_VCI_PTI_MODE … #define MID_VCI_MODE … #define MID_VCI_MODE_SHIFT … #define MID_VCI_READ … #define MID_VCI_READ_SHIFT … #define MID_VCI_DESCR … #define MID_VCI_DESCR_SHIFT … #define MID_VCI_COUNT … #define MID_VCI_COUNT_SHIFT … #define MID_VCI_STATE … #define MID_VCI_STATE_SHIFT … #define MID_VCI_WRITE … #define MID_VCI_WRITE_SHIFT … #define MID_MODE_TRASH … #define MID_MODE_RAW … #define MID_MODE_AAL5 … /* * Reassembly buffer descriptor */ #define MID_RED_COUNT … #define MID_RED_CRC_ERR … #define MID_RED_T … #define MID_RED_CE … #define MID_RED_CLP … #define MID_RED_IDEN … #define MID_RED_SHIFT … #define MID_RED_RX_ID … /* * Segmentation buffer descriptor */ #define MID_SEG_COUNT … #define MID_SEG_RATE … #define MID_SEG_RATE_SHIFT … #define MID_SEG_PR … #define MID_SEG_PR_SHIFT … #define MID_SEG_AAL5 … #define MID_SEG_ID … #define MID_SEG_ID_SHIFT … #define MID_SEG_MAX_RATE … #define MID_SEG_CLP … #define MID_SEG_PTI … #define MID_SEG_PTI_SHIFT … #define MID_SEG_VCI … #define MID_SEG_VCI_SHIFT … #define MID_SEG_TX_ID … /* * DMA entry */ #define MID_DMA_COUNT … #define MID_DMA_COUNT_SHIFT … #define MID_DMA_END … #define MID_DMA_TYPE … #define MID_DT_JK … #define MID_DT_WORD … #define MID_DT_2W … #define MID_DT_4W … #define MID_DT_8W … #define MID_DT_16W … #define MID_DT_2WM … #define MID_DT_4WM … #define MID_DT_8WM … #define MID_DT_16WM … /* only for RX*/ #define MID_DMA_VCI … #define MID_DMA_VCI_SHIFT … /* only for TX */ #define MID_DMA_CHAN … #define MID_DMA_CHAN_SHIFT … #define MID_DT_BYTE … #define MID_DT_HWORD … #endif
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