/******************************************************************* * * Copyright (c) 2000 ATecoM GmbH * * The author may be reached at [email protected]. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. * *******************************************************************/ #ifndef _IDT77252_H #define _IDT77252_H … #include <linux/ptrace.h> #include <linux/skbuff.h> #include <linux/workqueue.h> #include <linux/mutex.h> /*****************************************************************************/ /* */ /* Makros */ /* */ /*****************************************************************************/ #define VPCI2VC(card, vpi, vci) … /*****************************************************************************/ /* */ /* DEBUGGING definitions */ /* */ /*****************************************************************************/ #define DBG_RAW_CELL … #define DBG_TINY … #define DBG_GENERAL … #define DBG_XGENERAL … #define DBG_INIT … #define DBG_DEINIT … #define DBG_INTERRUPT … #define DBG_OPEN_CONN … #define DBG_CLOSE_CONN … #define DBG_RX_DATA … #define DBG_TX_DATA … #ifdef CONFIG_ATM_IDT77252_DEBUG #define CPRINTK(args...) … #define OPRINTK(args...) … #define IPRINTK(args...) … #define INTPRINTK(args...) … #define DIPRINTK(args...) … #define TXPRINTK(args...) … #define RXPRINTK(args...) … #define XPRINTK(args...) … #define DPRINTK(args...) … #define NPRINTK(args...) … #define RPRINTK(args...) … #else #define CPRINTK … #define OPRINTK … #define IPRINTK … #define INTPRINTK … #define DIPRINTK … #define TXPRINTK … #define RXPRINTK … #define XPRINTK … #define DPRINTK … #define NPRINTK … #define RPRINTK … #endif #define SCHED_UBR0 … #define SCHED_UBR … #define SCHED_VBR … #define SCHED_ABR … #define SCHED_CBR … #define SCQFULL_TIMEOUT … /*****************************************************************************/ /* */ /* Free Buffer Queue Layout */ /* */ /*****************************************************************************/ #define SAR_FB_SIZE_0 … #define SAR_FB_SIZE_1 … #define SAR_FB_SIZE_2 … #define SAR_FB_SIZE_3 … #define SAR_FBQ0_LOW … #define SAR_FBQ0_HIGH … #define SAR_FBQ1_LOW … #define SAR_FBQ1_HIGH … #define SAR_FBQ2_LOW … #define SAR_FBQ2_HIGH … #define SAR_FBQ3_LOW … #define SAR_FBQ3_HIGH … #if 0 #define SAR_TST_RESERVED … #else #define SAR_TST_RESERVED … #endif #define TCT_CBR … #define TCT_UBR … #define TCT_VBR … #define TCT_ABR … #define TCT_TYPE … #define TCT_RR … #define TCT_LMCR … #define TCT_SCD_MASK … #define TCT_TSIF … #define TCT_HALT … #define TCT_IDLE … #define TCT_FLAG_UBR … /*****************************************************************************/ /* */ /* Structure describing an IDT77252 */ /* */ /*****************************************************************************/ struct scqe { … }; #define SCQ_ENTRIES … #define SCQ_SIZE … #define SCQ_MASK … struct scq_info { … }; struct rx_pool { … }; struct aal1 { … }; struct vc_map; struct rate_estimator { … }; struct vc_map { … }; /*****************************************************************************/ /* */ /* RCTE - Receive Connection Table Entry */ /* */ /*****************************************************************************/ struct rct_entry { … }; /*****************************************************************************/ /* */ /* RSQ - Receive Status Queue */ /* */ /*****************************************************************************/ #define SAR_RSQE_VALID … #define SAR_RSQE_IDLE … #define SAR_RSQE_BUF_MASK … #define SAR_RSQE_BUF_ASGN … #define SAR_RSQE_NZGFC … #define SAR_RSQE_EPDU … #define SAR_RSQE_BUF_CONT … #define SAR_RSQE_EFCIE … #define SAR_RSQE_CLP … #define SAR_RSQE_CRC … #define SAR_RSQE_CELLCNT … #define RSQSIZE … #define RSQ_NUM_ENTRIES … #define RSQ_ALIGNMENT … struct rsq_entry { … }; struct rsq_info { … }; /*****************************************************************************/ /* */ /* TSQ - Transmit Status Queue */ /* */ /*****************************************************************************/ #define SAR_TSQE_INVALID … #define SAR_TSQE_TIMESTAMP … #define SAR_TSQE_TYPE … #define SAR_TSQE_TYPE_TIMER … #define SAR_TSQE_TYPE_TSR … #define SAR_TSQE_TYPE_IDLE … #define SAR_TSQE_TYPE_TBD_COMP … #define SAR_TSQE_TAG(stat) … #define TSQSIZE … #define TSQ_NUM_ENTRIES … #define TSQ_ALIGNMENT … struct tsq_entry { … }; struct tsq_info { … }; struct tst_info { … }; #define TSTE_MASK … #define TSTE_OPC_MASK … #define TSTE_OPC_NULL … #define TSTE_OPC_CBR … #define TSTE_OPC_VAR … #define TSTE_OPC_JMP … #define TSTE_PUSH_IDLE … #define TSTE_PUSH_ACTIVE … #define TST_SWITCH_DONE … #define TST_SWITCH_PENDING … #define TST_SWITCH_WAIT … #define FBQ_SHIFT … #define FBQ_SIZE … #define FBQ_MASK … struct sb_pool { … }; #define POOL_HANDLE(queue, index) … #define POOL_QUEUE(handle) … #define POOL_INDEX(handle) … struct idt77252_dev { … }; /* definition for flag field above */ #define IDT77252_BIT_INIT … #define IDT77252_BIT_INTERRUPT … #define ATM_CELL_PAYLOAD … #define FREEBUF_ALIGNMENT … /*****************************************************************************/ /* */ /* Makros */ /* */ /*****************************************************************************/ #define ALIGN_ADDRESS(addr, alignment) … /*****************************************************************************/ /* */ /* ABR SAR Network operation Register */ /* */ /*****************************************************************************/ #define SAR_REG_DR0 … #define SAR_REG_DR1 … #define SAR_REG_DR2 … #define SAR_REG_DR3 … #define SAR_REG_CMD … #define SAR_REG_CFG … #define SAR_REG_STAT … #define SAR_REG_RSQB … #define SAR_REG_RSQT … #define SAR_REG_RSQH … #define SAR_REG_CDC … #define SAR_REG_VPEC … #define SAR_REG_ICC … #define SAR_REG_RAWCT … #define SAR_REG_TMR … #define SAR_REG_TSTB … #define SAR_REG_TSQB … #define SAR_REG_TSQT … #define SAR_REG_TSQH … #define SAR_REG_GP … #define SAR_REG_VPM … #define SAR_REG_RXFD … #define SAR_REG_RXFT … #define SAR_REG_RXFH … #define SAR_REG_RAWHND … #define SAR_REG_RXSTAT … #define SAR_REG_ABRSTD … #define SAR_REG_ABRRQ … #define SAR_REG_VBRRQ … #define SAR_REG_RTBL … #define SAR_REG_MDFCT … #define SAR_REG_TXSTAT … #define SAR_REG_TCMDQ … #define SAR_REG_IRCP … #define SAR_REG_FBQP0 … #define SAR_REG_FBQP1 … #define SAR_REG_FBQP2 … #define SAR_REG_FBQP3 … #define SAR_REG_FBQS0 … #define SAR_REG_FBQS1 … #define SAR_REG_FBQS2 … #define SAR_REG_FBQS3 … #define SAR_REG_FBQWP0 … #define SAR_REG_FBQWP1 … #define SAR_REG_FBQWP2 … #define SAR_REG_FBQWP3 … #define SAR_REG_NOW … /*****************************************************************************/ /* */ /* Commands */ /* */ /*****************************************************************************/ #define SAR_CMD_NO_OPERATION … #define SAR_CMD_OPENCLOSE_CONNECTION … #define SAR_CMD_WRITE_SRAM … #define SAR_CMD_READ_SRAM … #define SAR_CMD_READ_UTILITY … #define SAR_CMD_WRITE_UTILITY … #define SAR_CMD_OPEN_CONNECTION … #define SAR_CMD_CLOSE_CONNECTION … /*****************************************************************************/ /* */ /* Configuration Register bits */ /* */ /*****************************************************************************/ #define SAR_CFG_SWRST … #define SAR_CFG_LOOP … #define SAR_CFG_RXPTH … #define SAR_CFG_IDLE_CLP … #define SAR_CFG_TX_FIFO_SIZE_1 … #define SAR_CFG_TX_FIFO_SIZE_2 … #define SAR_CFG_TX_FIFO_SIZE_4 … #define SAR_CFG_TX_FIFO_SIZE_9 … #define SAR_CFG_NO_IDLE … #define SAR_CFG_RSVD1 … #define SAR_CFG_RXSTQ_SIZE_2k … #define SAR_CFG_RXSTQ_SIZE_4k … #define SAR_CFG_RXSTQ_SIZE_8k … #define SAR_CFG_RXSTQ_SIZE_R … #define SAR_CFG_ICAPT … #define SAR_CFG_IGGFC … #define SAR_CFG_VPVCS_0 … #define SAR_CFG_VPVCS_1 … #define SAR_CFG_VPVCS_2 … #define SAR_CFG_VPVCS_8 … #define SAR_CFG_CNTBL_1k … #define SAR_CFG_CNTBL_4k … #define SAR_CFG_CNTBL_16k … #define SAR_CFG_CNTBL_512 … #define SAR_CFG_VPECA … #define SAR_CFG_RXINT_NOINT … #define SAR_CFG_RXINT_NODELAY … #define SAR_CFG_RXINT_256US … #define SAR_CFG_RXINT_505US … #define SAR_CFG_RXINT_742US … #define SAR_CFG_RAWIE … #define SAR_CFG_RQFIE … #define SAR_CFG_RSVD2 … #define SAR_CFG_CACHE … #define SAR_CFG_TMOIE … #define SAR_CFG_FBIE … #define SAR_CFG_TXEN … #define SAR_CFG_TXINT … #define SAR_CFG_TXUIE … #define SAR_CFG_UMODE … #define SAR_CFG_TXSFI … #define SAR_CFG_PHYIE … #define SAR_CFG_TX_FIFO_SIZE_MASK … #define SAR_CFG_RXSTQSIZE_MASK … #define SAR_CFG_CNTBL_MASK … #define SAR_CFG_RXINT_MASK … /*****************************************************************************/ /* */ /* Status Register bits */ /* */ /*****************************************************************************/ #define SAR_STAT_FRAC_3 … #define SAR_STAT_FRAC_2 … #define SAR_STAT_FRAC_1 … #define SAR_STAT_FRAC_0 … #define SAR_STAT_TSIF … #define SAR_STAT_TXICP … #define SAR_STAT_RSVD1 … #define SAR_STAT_TSQF … #define SAR_STAT_TMROF … #define SAR_STAT_PHYI … #define SAR_STAT_CMDBZ … #define SAR_STAT_FBQ3A … #define SAR_STAT_FBQ2A … #define SAR_STAT_RSQF … #define SAR_STAT_EPDU … #define SAR_STAT_RAWCF … #define SAR_STAT_FBQ1A … #define SAR_STAT_FBQ0A … #define SAR_STAT_RSQAF … #define SAR_STAT_RSVD2 … /*****************************************************************************/ /* */ /* General Purpose Register bits */ /* */ /*****************************************************************************/ #define SAR_GP_TXNCC_MASK … #define SAR_GP_EEDI … #define SAR_GP_BIGE … #define SAR_GP_RM_NORMAL … #define SAR_GP_RM_TO_RCQ … #define SAR_GP_RM_RSVD … #define SAR_GP_RM_INHIBIT … #define SAR_GP_PHY_RESET … #define SAR_GP_EESCLK … #define SAR_GP_EECS … #define SAR_GP_EEDO … /*****************************************************************************/ /* */ /* SAR local SRAM layout for 128k work SRAM */ /* */ /*****************************************************************************/ #define SAR_SRAM_SCD_SIZE … #define SAR_SRAM_TCT_SIZE … #define SAR_SRAM_RCT_SIZE … #define SAR_SRAM_TCT_128_BASE … #define SAR_SRAM_TCT_128_TOP … #define SAR_SRAM_RCT_128_BASE … #define SAR_SRAM_RCT_128_TOP … #define SAR_SRAM_FB0_128_BASE … #define SAR_SRAM_FB0_128_TOP … #define SAR_SRAM_FB1_128_BASE … #define SAR_SRAM_FB1_128_TOP … #define SAR_SRAM_FB2_128_BASE … #define SAR_SRAM_FB2_128_TOP … #define SAR_SRAM_FB3_128_BASE … #define SAR_SRAM_FB3_128_TOP … #define SAR_SRAM_SCD_128_BASE … #define SAR_SRAM_SCD_128_TOP … #define SAR_SRAM_TST1_128_BASE … #define SAR_SRAM_TST1_128_TOP … #define SAR_SRAM_TST2_128_BASE … #define SAR_SRAM_TST2_128_TOP … #define SAR_SRAM_ABRSTD_128_BASE … #define SAR_SRAM_ABRSTD_128_TOP … #define SAR_SRAM_RT_128_BASE … #define SAR_SRAM_RT_128_TOP … #define SAR_SRAM_FIFO_128_BASE … #define SAR_SRAM_FIFO_128_TOP … /*****************************************************************************/ /* */ /* SAR local SRAM layout for 32k work SRAM */ /* */ /*****************************************************************************/ #define SAR_SRAM_TCT_32_BASE … #define SAR_SRAM_TCT_32_TOP … #define SAR_SRAM_RCT_32_BASE … #define SAR_SRAM_RCT_32_TOP … #define SAR_SRAM_FB0_32_BASE … #define SAR_SRAM_FB0_32_TOP … #define SAR_SRAM_FB1_32_BASE … #define SAR_SRAM_FB1_32_TOP … #define SAR_SRAM_FB2_32_BASE … #define SAR_SRAM_FB2_32_TOP … #define SAR_SRAM_FB3_32_BASE … #define SAR_SRAM_FB3_32_TOP … #define SAR_SRAM_SCD_32_BASE … #define SAR_SRAM_SCD_32_TOP … #define SAR_SRAM_TST1_32_BASE … #define SAR_SRAM_TST1_32_TOP … #define SAR_SRAM_TST2_32_BASE … #define SAR_SRAM_TST2_32_TOP … #define SAR_SRAM_ABRSTD_32_BASE … #define SAR_SRAM_ABRSTD_32_TOP … #define SAR_SRAM_RT_32_BASE … #define SAR_SRAM_RT_32_TOP … #define SAR_SRAM_FIFO_32_BASE … #define SAR_SRAM_FIFO_32_TOP … /*****************************************************************************/ /* */ /* TSR - Transmit Status Request */ /* */ /*****************************************************************************/ #define SAR_TSR_TYPE_TSR … #define SAR_TSR_TYPE_TBD … #define SAR_TSR_TSIF … #define SAR_TSR_TAG_MASK … /*****************************************************************************/ /* */ /* TBD - Transmit Buffer Descriptor */ /* */ /*****************************************************************************/ #define SAR_TBD_EPDU … #define SAR_TBD_TSIF … #define SAR_TBD_OAM … #define SAR_TBD_AAL0 … #define SAR_TBD_AAL34 … #define SAR_TBD_AAL5 … #define SAR_TBD_GTSI … #define SAR_TBD_TAG_MASK … #define SAR_TBD_VPI_MASK … #define SAR_TBD_VCI_MASK … #define SAR_TBD_VC_MASK … #define SAR_TBD_VPI_SHIFT … #define SAR_TBD_VCI_SHIFT … /*****************************************************************************/ /* */ /* RXFD - Receive FIFO Descriptor */ /* */ /*****************************************************************************/ #define SAR_RXFD_SIZE_MASK … #define SAR_RXFD_SIZE_512 … #define SAR_RXFD_SIZE_1K … #define SAR_RXFD_SIZE_2K … #define SAR_RXFD_SIZE_4K … #define SAR_RXFD_SIZE_8K … #define SAR_RXFD_SIZE_16K … #define SAR_RXFD_SIZE_32K … #define SAR_RXFD_SIZE_64K … #define SAR_RXFD_SIZE_128K … #define SAR_RXFD_SIZE_256K … #define SAR_RXFD_ADDR_MASK … /*****************************************************************************/ /* */ /* ABRSTD - ABR + VBR Schedule Tables */ /* */ /*****************************************************************************/ #define SAR_ABRSTD_SIZE_MASK … #define SAR_ABRSTD_SIZE_512 … #define SAR_ABRSTD_SIZE_1K … #define SAR_ABRSTD_SIZE_2K … #define SAR_ABRSTD_SIZE_4K … #define SAR_ABRSTD_SIZE_8K … #define SAR_ABRSTD_SIZE_16K … #define SAR_ABRSTD_ADDR_MASK … /*****************************************************************************/ /* */ /* RCTE - Receive Connection Table Entry */ /* */ /*****************************************************************************/ #define SAR_RCTE_IL_MASK … #define SAR_RCTE_IC_MASK … #define SAR_RCTE_RSVD … #define SAR_RCTE_LCD … #define SAR_RCTE_CI_VC … #define SAR_RCTE_FBP_01 … #define SAR_RCTE_FBP_1 … #define SAR_RCTE_FBP_2 … #define SAR_RCTE_FBP_3 … #define SAR_RCTE_NZ_GFC … #define SAR_RCTE_CONNECTOPEN … #define SAR_RCTE_AAL_MASK … #define SAR_RCTE_RAWCELLINTEN … #define SAR_RCTE_RXCONCELLADDR … #define SAR_RCTE_BUFFSTAT_MASK … #define SAR_RCTE_EFCI … #define SAR_RCTE_CLP … #define SAR_RCTE_CRC … #define SAR_RCTE_CELLCNT_MASK … #define SAR_RCTE_AAL0 … #define SAR_RCTE_AAL34 … #define SAR_RCTE_AAL5 … #define SAR_RCTE_RCQ … #define SAR_RCTE_OAM … #define TCMDQ_START … #define TCMDQ_LACR … #define TCMDQ_START_LACR … #define TCMDQ_INIT_ER … #define TCMDQ_HALT … struct idt77252_skb_prv { … } __packed; #define IDT77252_PRV_TBD(skb) … #define IDT77252_PRV_PADDR(skb) … #define IDT77252_PRV_POOL(skb) … /*****************************************************************************/ /* */ /* PCI related items */ /* */ /*****************************************************************************/ #ifndef PCI_VENDOR_ID_IDT #define PCI_VENDOR_ID_IDT … #endif /* PCI_VENDOR_ID_IDT */ #ifndef PCI_DEVICE_ID_IDT_IDT77252 #define PCI_DEVICE_ID_IDT_IDT77252 … #endif /* PCI_DEVICE_ID_IDT_IDT772052 */ #endif /* !(_IDT77252_H) */
Codebase Browser
linux