/****************************************************************************** Device driver for Interphase ATM PCI adapter cards Author: Peter Wang <[email protected]> Interphase Corporation <www.iphase.com> Version: 1.0 iphase.h: This is the header file for iphase.c. ******************************************************************************* This software may be used and distributed according to the terms of the GNU General Public License (GPL), incorporated herein by reference. Drivers based on this skeleton fall under the GPL and must retain the authorship (implicit copyright) notice. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. Modified from an incomplete driver for Interphase 5575 1KVC 1M card which was originally written by Monalisa Agrawal at UNH. Now this driver supports a variety of varients of Interphase ATM PCI (i)Chip adapter card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM) in terms of PHY type, the size of control memory and the size of packet memory. The following are the change log and history: Bugfix the Mona's UBR driver. Modify the basic memory allocation and dma logic. Port the driver to the latest kernel from 2.0.46. Complete the ABR logic of the driver, and added the ABR work- around for the hardware anormalies. Add the CBR support. Add the flow control logic to the driver to allow rate-limit VC. Add 4K VC support to the board with 512K control memory. Add the support of all the variants of the Interphase ATM PCI (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525 (25M UTP25) and x531 (DS3 and E3). Add SMP support. Support and updates available at: ftp://ftp.iphase.com/pub/atm *******************************************************************************/ #ifndef IPHASE_H #define IPHASE_H /************************ IADBG DEFINE *********************************/ /* IADebugFlag Bit Map */ #define IF_IADBG_INIT_ADAPTER … #define IF_IADBG_TX … #define IF_IADBG_RX … #define IF_IADBG_QUERY_INFO … #define IF_IADBG_SHUTDOWN … #define IF_IADBG_INTR … #define IF_IADBG_TXPKT … #define IF_IADBG_RXPKT … #define IF_IADBG_ERR … #define IF_IADBG_EVENT … #define IF_IADBG_DIS_INTR … #define IF_IADBG_EN_INTR … #define IF_IADBG_LOUD … #define IF_IADBG_VERY_LOUD … #define IF_IADBG_CBR … #define IF_IADBG_UBR … #define IF_IADBG_ABR … #define IF_IADBG_DESC … #define IF_IADBG_SUNI_STAT … #define IF_IADBG_RESET … #define IF_IADBG(f) … #ifdef CONFIG_ATM_IA_DEBUG /* Debug build */ #define IF_LOUD(A) … #define IF_ERR(A) … #define IF_VERY_LOUD(A) … #define IF_INIT_ADAPTER(A) … #define IF_INIT(A) … #define IF_SUNI_STAT(A) … #define IF_QUERY_INFO(A) … #define IF_COPY_OVER(A) … #define IF_INTR(A) … #define IF_DIS_INTR(A) … #define IF_EN_INTR(A) … #define IF_TX(A) … #define IF_RX(A) … #define IF_TXPKT(A) … #define IF_RXPKT(A) … #define IF_SHUTDOWN(A) … #define IF_CBR(A) … #define IF_UBR(A) … #define IF_ABR(A) … #define IF_EVENT(A) … #else /* free build */ #define IF_LOUD … #define IF_VERY_LOUD … #define IF_INIT_ADAPTER … #define IF_INIT … #define IF_SUNI_STAT … #define IF_PVC_CHKPKT … #define IF_QUERY_INFO … #define IF_COPY_OVER … #define IF_HANG … #define IF_INTR … #define IF_DIS_INTR … #define IF_EN_INTR … #define IF_TX … #define IF_RX … #define IF_TXDEBUG … #define IF_VC … #define IF_ERR … #define IF_CBR … #define IF_UBR … #define IF_ABR … #define IF_SHUTDOWN … #define DbgPrint … #define IF_EVENT … #define IF_TXPKT … #define IF_RXPKT … #endif /* CONFIG_ATM_IA_DEBUG */ #define ATM_DESC(skb) … #define IA_SKB_STATE(skb) … #define IA_DLED … #define IA_TX_DONE … /* iadbg defines */ #define IA_CMD … PIA_CMDBUF; /* cmds */ #define MEMDUMP … /* sub_cmds */ #define MEMDUMP_SEGREG … #define MEMDUMP_DEV … #define MEMDUMP_REASSREG … #define MEMDUMP_FFL … #define READ_REG … #define WAKE_DBG_WAIT … /************************ IADBG DEFINE END ***************************/ #define Boolean(x) … #define NR_VCI … #define NR_VCI_LD … #define NR_VCI_4K … #define NR_VCI_4K_LD … #define MEM_VALID … #ifndef PCI_VENDOR_ID_IPHASE #define PCI_VENDOR_ID_IPHASE … #endif #ifndef PCI_DEVICE_ID_IPHASE_5575 #define PCI_DEVICE_ID_IPHASE_5575 … #endif #define DEV_LABEL … #define PCR … #define ICR … #define MCR … #define TBE … #define FRTT … #define RIF … #define RDF … #define NRMCODE … #define TRMCODE … #define CDFCODE … #define ATDFCODE … /*---------------------- Packet/Cell Memory ------------------------*/ #define TX_PACKET_RAM … #define DFL_TX_BUF_SZ … #define DFL_TX_BUFFERS … #define REASS_RAM_SIZE … #define RX_PACKET_RAM … #define DFL_RX_BUF_SZ … #define DFL_RX_BUFFERS … struct cpcs_trailer { … }; struct cpcs_trailer_desc { … }; struct ia_vcc { … }; struct abr_vc_table { … }; /* 32 byte entries */ struct main_vc { … }; /* 8 byte entries */ struct ext_vc { … }; #define DLE_ENTRIES … #define DMA_INT_ENABLE … #define TX_DLE_PSI … #define DLE_TOTAL_SIZE … /* Descriptor List Entries (DLE) */ struct dle { … }; struct dle_q { … }; struct free_desc_q { … }; struct tx_buf_desc { … }; struct rx_buf_desc { … }; /*--------SAR stuff ---------------------*/ #define EPROM_SIZE … #define MAC1_LEN … #define MAC2_LEN … /*------------ PCI Memory Space Map, 128K SAR memory ----------------*/ #define IPHASE5575_PCI_CONFIG_REG_BASE … #define IPHASE5575_BUS_CONTROL_REG_BASE … #define IPHASE5575_FRAG_CONTROL_REG_BASE … #define IPHASE5575_REASS_CONTROL_REG_BASE … #define IPHASE5575_DMA_CONTROL_REG_BASE … #define IPHASE5575_FRONT_END_REG_BASE … #define IPHASE5575_FRAG_CONTROL_RAM_BASE … #define IPHASE5575_REASS_CONTROL_RAM_BASE … /*------------ Bus interface control registers -----------------*/ #define IPHASE5575_BUS_CONTROL_REG … #define IPHASE5575_BUS_STATUS_REG … #define IPHASE5575_MAC1 … #define IPHASE5575_REV … #define IPHASE5575_MAC2 … #define IPHASE5575_EXT_RESET … #define IPHASE5575_INT_RESET … #define IPHASE5575_PCI_ADDR_PAGE … #define IPHASE5575_EEPROM_ACCESS … #define IPHASE5575_CELL_FIFO_QUEUE_SZ … #define IPHASE5575_CELL_FIFO_MARK_STATE … #define IPHASE5575_CELL_FIFO_READ_PTR … #define IPHASE5575_CELL_FIFO_WRITE_PTR … #define IPHASE5575_CELL_FIFO_CELLS_AVL … /* Bus Interface Control Register bits */ #define CTRL_FE_RST … #define CTRL_LED … #define CTRL_25MBPHY … #define CTRL_ENCMBMEM … #define CTRL_ENOFFSEG … #define CTRL_ERRMASK … #define CTRL_DLETMASK … #define CTRL_DLERMASK … #define CTRL_FEMASK … #define CTRL_SEGMASK … #define CTRL_REASSMASK … #define CTRL_CSPREEMPT … #define CTRL_B128 … #define CTRL_B64 … #define CTRL_B48 … #define CTRL_B32 … #define CTRL_B16 … #define CTRL_B8 … /* Bus Interface Status Register bits */ #define STAT_CMEMSIZ … #define STAT_ADPARCK … #define STAT_RESVD … #define STAT_ERRINT … #define STAT_MARKINT … #define STAT_DLETINT … #define STAT_DLERINT … #define STAT_FEINT … #define STAT_SEGINT … #define STAT_REASSINT … /*--------------- Segmentation control registers -----------------*/ /* The segmentation registers are 16 bits access and the addresses are defined as such so the addresses are the actual "offsets" */ #define IDLEHEADHI … #define IDLEHEADLO … #define MAXRATE … /* Values for MAXRATE register for 155Mbps and 25.6 Mbps operation */ #define RATE155 … #define MAX_ATM_155 … #define RATE25 … #define STPARMS … #define STPARMS_1K … #define STPARMS_2K … #define STPARMS_4K … #define COMP_EN … #define CBR_EN … #define ABR_EN … #define UBR_EN … #define ABRUBR_ARB … #define RM_TYPE … /*Value for RM_TYPE register for ATM Forum Traffic Mangement4.0 support*/ #define RM_TYPE_4_0 … #define SEG_COMMAND_REG … /* Values for the command register */ #define RESET_SEG … #define RESET_SEG_STATE … #define RESET_TX_CELL_CTR … #define CBR_PTR_BASE … #define ABR_SBPTR_BASE … #define UBR_SBPTR_BASE … #define ABRWQ_BASE … #define UBRWQ_BASE … #define VCT_BASE … #define VCTE_BASE … #define CBR_TAB_BEG … #define CBR_TAB_END … #define PRQ_ST_ADR … #define PRQ_ED_ADR … #define PRQ_RD_PTR … #define PRQ_WR_PTR … #define TCQ_ST_ADR … #define TCQ_ED_ADR … #define TCQ_RD_PTR … #define TCQ_WR_PTR … #define SEG_QUEUE_BASE … #define SEG_DESC_BASE … #define MODE_REG_0 … #define T_ONLINE … #define MODE_REG_1 … #define MODE_REG_1_VAL … #define SEG_INTR_STATUS_REG … #define SEG_MASK_REG … #define TRANSMIT_DONE … #define TCQ_NOT_EMPTY … #define CELL_CTR_HIGH_AUTO … #define CELL_CTR_HIGH_NOAUTO … #define CELL_CTR_LO_AUTO … #define CELL_CTR_LO_NOAUTO … /* Diagnostic registers */ #define NEXTDESC … #define NEXTVC … #define PSLOTCNT … #define NEWDN … #define NEWVC … #define SBPTR … #define ABRWQ_WRPTR … #define ABRWQ_RDPTR … #define UBRWQ_WRPTR … #define UBRWQ_RDPTR … #define CBR_VC … #define ABR_SBVC … #define UBR_SBVC … #define ABRNEXTLINK … #define UBRNEXTLINK … /*----------------- Reassembly control registers ---------------------*/ /* The reassembly registers are 16 bits access and the addresses are defined as such so the addresses are the actual "offsets" */ #define MODE_REG … #define R_ONLINE … #define IGN_RAW_FL … #define PROTOCOL_ID … #define REASS_MASK_REG … #define REASS_INTR_STATUS_REG … /* Interrupt Status register bits */ #define RX_PKT_CTR_OF … #define RX_ERR_CTR_OF … #define RX_CELL_CTR_OF … #define RX_FREEQ_EMPT … #define RX_EXCPQ_FL … #define RX_RAWQ_FL … #define RX_EXCP_RCVD … #define RX_PKT_RCVD … #define RX_RAW_RCVD … #define DRP_PKT_CNTR … #define ERR_CNTR … #define RAW_BASE_ADR … #define CELL_CTR0 … #define CELL_CTR1 … #define REASS_COMMAND_REG … /* Values for command register */ #define RESET_REASS … #define RESET_REASS_STATE … #define RESET_DRP_PKT_CNTR … #define RESET_ERR_CNTR … #define RESET_CELL_CNTR … #define RESET_REASS_ALL_REGS … #define REASS_DESC_BASE … #define VC_LKUP_BASE … #define REASS_TABLE_BASE … #define REASS_QUEUE_BASE … #define PKT_TM_CNT … #define TMOUT_RANGE … #define INTRVL_CNTR … #define TMOUT_INDX … #define VP_LKUP_BASE … #define VP_FILTER … #define ABR_LKUP_BASE … #define FREEQ_ST_ADR … #define FREEQ_ED_ADR … #define FREEQ_RD_PTR … #define FREEQ_WR_PTR … #define PCQ_ST_ADR … #define PCQ_ED_ADR … #define PCQ_RD_PTR … #define PCQ_WR_PTR … #define EXCP_Q_ST_ADR … #define EXCP_Q_ED_ADR … #define EXCP_Q_RD_PTR … #define EXCP_Q_WR_PTR … #define CC_FIFO_ST_ADR … #define CC_FIFO_ED_ADR … #define CC_FIFO_RD_PTR … #define CC_FIFO_WR_PTR … #define STATE_REG … #define BUF_SIZE … #define XTRA_RM_OFFSET … #define DRP_PKT_CNTR_NC … #define ERR_CNTR_NC … #define CELL_CNTR0_NC … #define CELL_CNTR1_NC … /* State Register bits */ #define EXCPQ_EMPTY … #define PCQ_EMPTY … #define FREEQ_EMPTY … /*----------------- Front End registers/ DMA control --------------*/ /* There is a lot of documentation error regarding these offsets ??? eg:- 2 offsets given 800, a00 for rx counter similarly many others Remember again that the offsets are to be 4*register number, so correct the #defines here */ #define IPHASE5575_TX_COUNTER … #define IPHASE5575_RX_COUNTER … #define IPHASE5575_TX_LIST_ADDR … #define IPHASE5575_RX_LIST_ADDR … /*--------------------------- RAM ---------------------------*/ /* These memory maps are actually offsets from the segmentation and reassembly RAM base addresses */ /* Segmentation Control Memory map */ #define TX_DESC_BASE … #define TX_COMP_Q … #define PKT_RDY_Q … #define CBR_SCHED_TABLE … #define UBR_SCHED_TABLE … #define UBR_WAIT_Q … #define ABR_SCHED_TABLE … #define ABR_WAIT_Q … #define EXT_VC_TABLE … #define MAIN_VC_TABLE … #define SCHEDSZ … #define TX_DESC_TABLE_SZ … /* These are used as table offsets in Descriptor Table address generation */ #define DESC_MODE … #define VC_INDEX … #define BYTE_CNT … #define PKT_START_HI … #define PKT_START_LO … /* Descriptor Mode Word Bits */ #define EOM_EN … #define AAL5 … #define APP_CRC32 … #define CMPL_INT … #define TABLE_ADDRESS(db, dn, to) … /* Reassembly Control Memory Map */ #define RX_DESC_BASE … #define VP_TABLE … #define EXCEPTION_Q … #define FREE_BUF_DESC_Q … #define PKT_COMP_Q … #define REASS_TABLE … #define RX_VC_TABLE … #define ABR_VC_TABLE … #define RX_DESC_TABLE_SZ … #define VP_TABLE_SZ … #define RX_VC_TABLE_SZ … #define REASS_TABLE_SZ … /* Buffer Descriptor Table */ #define RX_ACT … #define RX_VPVC … #define RX_CNG … #define RX_CER … #define RX_PTE … #define RX_OFL … #define NUM_RX_EXCP … /* Reassembly Table */ #define NO_AAL5_PKT … #define AAL5_PKT_REASSEMBLED … #define AAL5_PKT_TERMINATED … #define RAW_PKT … #define REASS_ABR … /*-------------------- Base Registers --------------------*/ #define REG_BASE … #define RAM_BASE … #define PHY_BASE … #define SEG_BASE … #define REASS_BASE … ffreg_t; rreg_t; ffredn_t; rfredn_t; ia_regs_t; f_vc_abr_entry; r_vc_abr_entry; #define MRM … srv_cls_param_t; struct testTable_t { … }; RX_ERROR_Q; vcstatus_t; struct ia_rfL_t { … }; struct ia_ffL_t { … }; struct desc_tbl_t { … }; IARTN_Q; #define SUNI_LOSV … enum ia_suni { … }; IA_SUNI_STATS; IADEV; #define INPH_IA_DEV(d) … #define INPH_IA_VCC(v) … /******************* IDT77105 25MB/s PHY DEFINE *****************************/ enum ia_mb25 { … }; /* * Master Control */ #define MB25_MC_UPLO … #define MB25_MC_DREC … #define MB25_MC_ECEIO … #define MB25_MC_TDPC … #define MB25_MC_DRIC … #define MB25_MC_HALTTX … #define MB25_MC_UMS … #define MB25_MC_ENABLED … /* * Interrupt Status */ #define MB25_IS_GSB … #define MB25_IS_HECECR … #define MB25_IS_SCR … #define MB25_IS_TPE … #define MB25_IS_RSCC … #define MB25_IS_RCSE … #define MB25_IS_RFIFOO … /* * Diagnostic Control */ #define MB25_DC_FTXCD … #define MB25_DC_RXCOS … #define MB25_DC_ECEIO … #define MB25_DC_RLFLUSH … #define MB25_DC_IXPE … #define MB25_DC_IXHECE … #define MB25_DC_LB_MASK … #define MB25_DC_LL … #define MB25_DC_PL … #define MB25_DC_NM … #define FE_MASK … #define FE_MULTI_MODE … #define FE_SINGLE_MODE … #define FE_UTP_OPTION … #define FE_25MBIT_PHY … #define FE_DS3_PHY … #define FE_E3_PHY … /*********************** SUNI_PM7345 PHY DEFINE HERE *********************/ enum suni_pm7345 { … }; #define SUNI_PM7345_T … #define SUNI_PM7345 … #define SUNI_PM5346 … /* * SUNI_PM7345 Configuration */ #define SUNI_PM7345_CLB … #define SUNI_PM7345_PLB … #define SUNI_PM7345_DLB … #define SUNI_PM7345_LLB … #define SUNI_PM7345_E3ENBL … #define SUNI_PM7345_LOOPT … #define SUNI_PM7345_FIFOBP … #define SUNI_PM7345_FRMRBP … /* * DS3 FRMR Interrupt Enable */ #define SUNI_DS3_COFAE … #define SUNI_DS3_REDE … #define SUNI_DS3_CBITE … #define SUNI_DS3_FERFE … #define SUNI_DS3_IDLE … #define SUNI_DS3_AISE … #define SUNI_DS3_OOFE … #define SUNI_DS3_LOSE … /* * DS3 FRMR Status */ #define SUNI_DS3_ACE … #define SUNI_DS3_REDV … #define SUNI_DS3_CBITV … #define SUNI_DS3_FERFV … #define SUNI_DS3_IDLV … #define SUNI_DS3_AISV … #define SUNI_DS3_OOFV … #define SUNI_DS3_LOSV … /* * E3 FRMR Interrupt/Status */ #define SUNI_E3_CZDI … #define SUNI_E3_LOSI … #define SUNI_E3_LCVI … #define SUNI_E3_COFAI … #define SUNI_E3_OOFI … #define SUNI_E3_LOS … #define SUNI_E3_OOF … /* * E3 FRMR Maintenance Status */ #define SUNI_E3_AISD … #define SUNI_E3_FERF_RAI … #define SUNI_E3_FEBE … /* * RXCP Control/Status */ #define SUNI_DS3_HCSPASS … #define SUNI_DS3_HCSDQDB … #define SUNI_DS3_HCSADD … #define SUNI_DS3_HCK … #define SUNI_DS3_BLOCK … #define SUNI_DS3_DSCR … #define SUNI_DS3_OOCDV … #define SUNI_DS3_FIFORST … /* * RXCP Interrupt Enable/Status */ #define SUNI_DS3_OOCDE … #define SUNI_DS3_HCSE … #define SUNI_DS3_FIFOE … #define SUNI_DS3_OOCDI … #define SUNI_DS3_UHCSI … #define SUNI_DS3_COCAI … #define SUNI_DS3_FOVRI … #define SUNI_DS3_FUDRI … ///////////////////SUNI_PM7345 PHY DEFINE END ///////////////////////////// /* ia_eeprom define*/ #define MEM_SIZE_MASK … #define MEM_SIZE_128K … #define MEM_SIZE_512K … #define MEM_SIZE_1M … /* 0x3 to 0xF are reserved for future */ #define FE_MASK … #define FE_MULTI_MODE … #define FE_SINGLE_MODE … #define FE_UTP_OPTION … #define NOVRAM_SIZE … #define CMD_LEN … /*********** * * Switches and defines for header files. * * The following defines are used to turn on and off * various options in the header files. Primarily useful * for debugging. * ***********/ /* * a list of the commands that can be sent to the NOVRAM */ #define EXTEND … #define IAWRITE … #define IAREAD … #define ERASE … #define EWDS … #define WRAL … #define ERAL … #define EWEN … /* * these bits duplicate the hw_flip.h register settings * note: how the data in / out bits are defined in the flipper specification */ #define NVCE … #define NVSK … #define NVDO … #define NVDI … /*********************** * * This define ands the value and the current config register and puts * the result in the config register * ***********************/ #define CFG_AND(val) … /*********************** * * This define ors the value and the current config register and puts * the result in the config register * ***********************/ #define CFG_OR(val) … /*********************** * * Send a command to the NOVRAM, the command is in cmd. * * clear CE and SK. Then assert CE. * Clock each of the command bits out in the correct order with SK * exit with CE still asserted * ***********************/ #define NVRAM_CMD(cmd) … /*********************** * * clear the CE, this must be used after each command is complete * ***********************/ #define NVRAM_CLR_CE … /*********************** * * clock the data bit in bitval out to the NOVRAM. The bitval must be * a 1 or 0, or the clockout operation is undefined * ***********************/ #define NVRAM_CLKOUT(bitval) … /*********************** * * clock the data bit in and return a 1 or 0, depending on the value * that was received from the NOVRAM * ***********************/ #define NVRAM_CLKIN(value) … #endif /* IPHASE_H */
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