/****************************************************************************** iphase.c: Device driver for Interphase ATM PCI adapter cards Author: Peter Wang <[email protected]> Some fixes: Arnaldo Carvalho de Melo <[email protected]> Interphase Corporation <www.iphase.com> Version: 1.0 ******************************************************************************* This software may be used and distributed according to the terms of the GNU General Public License (GPL), incorporated herein by reference. Drivers based on this skeleton fall under the GPL and must retain the authorship (implicit copyright) notice. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. Modified from an incomplete driver for Interphase 5575 1KVC 1M card which was originally written by Monalisa Agrawal at UNH. Now this driver supports a variety of varients of Interphase ATM PCI (i)Chip adapter card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM) in terms of PHY type, the size of control memory and the size of packet memory. The following are the change log and history: Bugfix the Mona's UBR driver. Modify the basic memory allocation and dma logic. Port the driver to the latest kernel from 2.0.46. Complete the ABR logic of the driver, and added the ABR work- around for the hardware anormalies. Add the CBR support. Add the flow control logic to the driver to allow rate-limit VC. Add 4K VC support to the board with 512K control memory. Add the support of all the variants of the Interphase ATM PCI (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525 (25M UTP25) and x531 (DS3 and E3). Add SMP support. Support and updates available at: ftp://ftp.iphase.com/pub/atm *******************************************************************************/ #include <linux/module.h> #include <linux/kernel.h> #include <linux/mm.h> #include <linux/pci.h> #include <linux/errno.h> #include <linux/atm.h> #include <linux/atmdev.h> #include <linux/ctype.h> #include <linux/sonet.h> #include <linux/skbuff.h> #include <linux/time.h> #include <linux/delay.h> #include <linux/uio.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/wait.h> #include <linux/slab.h> #include <asm/io.h> #include <linux/atomic.h> #include <linux/uaccess.h> #include <asm/string.h> #include <asm/byteorder.h> #include <linux/vmalloc.h> #include <linux/jiffies.h> #include <linux/nospec.h> #include "iphase.h" #include "suni.h" #define swap_byte_order(x) … #define PRIV(dev) … static unsigned char ia_phy_get(struct atm_dev *dev, unsigned long addr); static void desc_dbg(IADEV *iadev); static IADEV *ia_dev[8]; static struct atm_dev *_ia_dev[8]; static int iadev_count; static void ia_led_timer(struct timer_list *unused); static DEFINE_TIMER(ia_timer, ia_led_timer); static int IA_TX_BUF = …, IA_TX_BUF_SZ = …; static int IA_RX_BUF = …, IA_RX_BUF_SZ = …; static uint IADebugFlag = …/* IF_IADBG_ERR | IF_IADBG_CBR| IF_IADBG_INIT_ADAPTER |IF_IADBG_ABR | IF_IADBG_EVENT*/ 0; module_param(IA_TX_BUF, int, 0); module_param(IA_TX_BUF_SZ, int, 0); module_param(IA_RX_BUF, int, 0); module_param(IA_RX_BUF_SZ, int, 0); module_param(IADebugFlag, uint, 0644); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; /**************************** IA_LIB **********************************/ static void ia_init_rtn_q (IARTN_Q *que) { … } static void ia_enque_head_rtn_q (IARTN_Q *que, IARTN_Q * data) { … } static int ia_enque_rtn_q (IARTN_Q *que, struct desc_tbl_t data) { … } static IARTN_Q * ia_deque_rtn_q (IARTN_Q *que) { … } static void ia_hack_tcq(IADEV *dev) { … } /* ia_hack_tcq */ static u16 get_desc (IADEV *dev, struct ia_vcc *iavcc) { … } static void clear_lockup (struct atm_vcc *vcc, IADEV *dev) { … } /* ** Conversion of 24-bit cellrate (cells/sec) to 16-bit floating point format. ** ** +----+----+------------------+-------------------------------+ ** | R | NZ | 5-bit exponent | 9-bit mantissa | ** +----+----+------------------+-------------------------------+ ** ** R = reserved (written as 0) ** NZ = 0 if 0 cells/sec; 1 otherwise ** ** if NZ = 1, rate = 1.mmmmmmmmm x 2^(eeeee) cells/sec */ static u16 cellrate_to_float(u32 cr) { … } #if 0 /* ** Conversion of 16-bit floating point format to 24-bit cellrate (cells/sec). */ static u32 float_to_cellrate(u16 rate) { u32 exp, mantissa, cps; if ((rate & NZ) == 0) return 0; exp = (rate >> M_BITS) & E_MASK; mantissa = rate & M_MASK; if (exp == 0) return 1; cps = (1 << M_BITS) | mantissa; if (exp == M_BITS) cps = cps; else if (exp > M_BITS) cps <<= (exp - M_BITS); else cps >>= (M_BITS - exp); return cps; } #endif static void init_abr_vc (IADEV *dev, srv_cls_param_t *srv_p) { … } static int ia_open_abr_vc(IADEV *dev, srv_cls_param_t *srv_p, struct atm_vcc *vcc, u8 flag) { … } static int ia_cbr_setup (IADEV *dev, struct atm_vcc *vcc) { … } static void ia_cbrVc_close (struct atm_vcc *vcc) { … } static int ia_avail_descs(IADEV *iadev) { … } static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb); static int ia_que_tx (IADEV *iadev) { … } static void ia_tx_poll (IADEV *iadev) { … } #if 0 static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val) { u32 t; int i; /* * Issue a command to enable writes to the NOVRAM */ NVRAM_CMD (EXTEND + EWEN); NVRAM_CLR_CE; /* * issue the write command */ NVRAM_CMD(IAWRITE + addr); /* * Send the data, starting with D15, then D14, and so on for 16 bits */ for (i=15; i>=0; i--) { NVRAM_CLKOUT (val & 0x8000); val <<= 1; } NVRAM_CLR_CE; CFG_OR(NVCE); t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); while (!(t & NVDO)) t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); NVRAM_CLR_CE; /* * disable writes again */ NVRAM_CMD(EXTEND + EWDS) NVRAM_CLR_CE; CFG_AND(~NVDI); } #endif static u16 ia_eeprom_get (IADEV *iadev, u32 addr) { … } static void ia_hw_type(IADEV *iadev) { … } static u32 ia_phy_read32(struct iadev_priv *ia, unsigned int reg) { … } static void ia_phy_write32(struct iadev_priv *ia, unsigned int reg, u32 val) { … } static void ia_frontend_intr(struct iadev_priv *iadev) { … } static void ia_mb25_init(struct iadev_priv *iadev) { … } struct ia_reg { … }; static void ia_phy_write(struct iadev_priv *iadev, const struct ia_reg *regs, int len) { … } static void ia_suni_pm7345_init_ds3(struct iadev_priv *iadev) { … } static void ia_suni_pm7345_init_e3(struct iadev_priv *iadev) { … } static void ia_suni_pm7345_init(struct iadev_priv *iadev) { … } /***************************** IA_LIB END *****************************/ #ifdef CONFIG_ATM_IA_DEBUG static int tcnter = …; static void xdump( u_char* cp, int length, char* prefix ) { … } /* close xdump(... */ #endif /* CONFIG_ATM_IA_DEBUG */ static struct atm_dev *ia_boards = …; #define ACTUAL_RAM_BASE … #define ACTUAL_SEG_RAM_BASE … #define ACTUAL_REASS_RAM_BASE … /*-- some utilities and memory allocation stuff will come here -------------*/ static void desc_dbg(IADEV *iadev) { … } /*----------------------------- Receiving side stuff --------------------------*/ static void rx_excp_rcvd(struct atm_dev *dev) { … } static void free_desc(struct atm_dev *dev, int desc) { … } static int rx_pkt(struct atm_dev *dev) { … } static void rx_intr(struct atm_dev *dev) { … } static void rx_dle_intr(struct atm_dev *dev) { … } static int open_rx(struct atm_vcc *vcc) { … } static int rx_init(struct atm_dev *dev) { … } /* The memory map suggested in appendix A and the coding for it. Keeping it around just in case we change our mind later. Buffer descr 0x0000 (128 - 4K) UBR sched 0x1000 (1K - 4K) UBR Wait q 0x2000 (1K - 4K) Commn queues 0x3000 Packet Ready, Trasmit comp(0x3100) (128 - 256) each extended VC 0x4000 (1K - 8K) ABR sched 0x6000 and ABR wait queue (1K - 2K) each CBR sched 0x7000 (as needed) VC table 0x8000 (1K - 32K) */ static void tx_intr(struct atm_dev *dev) { … } static void tx_dle_intr(struct atm_dev *dev) { … } static int open_tx(struct atm_vcc *vcc) { … } static int tx_init(struct atm_dev *dev) { … } static irqreturn_t ia_int(int irq, void *dev_id) { … } /*----------------------------- entries --------------------------------*/ static int get_esi(struct atm_dev *dev) { … } static int reset_sar(struct atm_dev *dev) { … } static int ia_init(struct atm_dev *dev) { … } static void ia_update_stats(IADEV *iadev) { … } static void ia_led_timer(struct timer_list *unused) { … } static void ia_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) { … } static unsigned char ia_phy_get(struct atm_dev *dev, unsigned long addr) { … } static void ia_free_tx(IADEV *iadev) { … } static void ia_free_rx(IADEV *iadev) { … } static int ia_start(struct atm_dev *dev) { … } static void ia_close(struct atm_vcc *vcc) { … } static int ia_open(struct atm_vcc *vcc) { … } static int ia_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) { … } static int ia_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg) { … } static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb) { … } static int ia_send(struct atm_vcc *vcc, struct sk_buff *skb) { … } static int ia_proc_read(struct atm_dev *dev,loff_t *pos,char *page) { … } static const struct atmdev_ops ops = …; static int ia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { … } static void ia_remove_one(struct pci_dev *pdev) { … } static const struct pci_device_id ia_pci_tbl[] = …; MODULE_DEVICE_TABLE(pci, ia_pci_tbl); static struct pci_driver ia_driver = …; static int __init ia_module_init(void) { … } static void __exit ia_module_exit(void) { … } module_init(…) …; module_exit(ia_module_exit);
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