/* he.h ForeRunnerHE ATM Adapter driver for ATM on Linux Copyright (C) 1999-2001 Naval Research Laboratory This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with this library; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ /* he.h ForeRunnerHE ATM Adapter driver for ATM on Linux Copyright (C) 1999-2000 Naval Research Laboratory Permission to use, copy, modify and distribute this software and its documentation is hereby granted, provided that both the copyright notice and this permission notice appear in all copies of the software, derivative works or modified versions, and any portions thereof, and that both notices appear in supporting documentation. NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. */ #ifndef _HE_H_ #define _HE_H_ #define DEV_LABEL … #define CONFIG_DEFAULT_VCIBITS … #define CONFIG_DEFAULT_VPIBITS … #define CONFIG_IRQ_SIZE … #define CONFIG_IRQ_THRESH … #define CONFIG_TPDRQ_SIZE … #define TPDRQ_MASK(x) … #define CONFIG_RBRQ_SIZE … #define CONFIG_RBRQ_THRESH … #define RBRQ_MASK(x) … #define CONFIG_TBRQ_SIZE … #define CONFIG_TBRQ_THRESH … #define TBRQ_MASK(x) … #define CONFIG_RBPL_SIZE … #define CONFIG_RBPL_THRESH … #define CONFIG_RBPL_BUFSIZE … #define RBPL_MASK(x) … /* 5.1.3 initialize connection memory */ #define CONFIG_RSRA … #define CONFIG_RCMLBM … #define CONFIG_RCMABR … #define CONFIG_RSRB … #define CONFIG_TSRA … #define CONFIG_TSRB … #define CONFIG_TSRC … #define CONFIG_TSRD … #define CONFIG_TMABR … #define CONFIG_TPDBA … #define HE_MAXCIDBITS … /* 2.9.3.3 interrupt encodings */ struct he_irq { … }; #define IRQ_ALIGNMENT … #define NEXT_ENTRY(base, tail, mask) … #define ITYPE_INVALID … #define ITYPE_TBRQ_THRESH … #define ITYPE_TPD_COMPLETE … #define ITYPE_RBPS_THRESH … #define ITYPE_RBPL_THRESH … #define ITYPE_RBRQ_THRESH … #define ITYPE_RBRQ_TIMER … #define ITYPE_PHY … #define ITYPE_OTHER … #define ITYPE_PARITY … #define ITYPE_ABORT … #define ITYPE_GROUP(x) … #define ITYPE_TYPE(x) … #define HE_NUM_GROUPS … /* 2.1.4 transmit packet descriptor */ struct he_tpd { … }; #define TPD_ALIGNMENT … #define TPD_LEN_MASK … #define TPD_ADDR_SHIFT … #define TPD_MASK … #define TPD_ADDR(x) … #define TPD_INDEX(x) … /* table 2.3 transmit buffer return elements */ struct he_tbrq { … }; #define TBRQ_ALIGNMENT … #define TBRQ_TPD(tbrq) … #define TBRQ_EOS(tbrq) … #define TBRQ_MULTIPLE(tbrq) … /* table 2.21 receive buffer return queue element field organization */ struct he_rbrq { … }; #define RBRQ_ALIGNMENT … #define RBRQ_ADDR(rbrq) … #define RBRQ_CRC_ERR(rbrq) … #define RBRQ_LEN_ERR(rbrq) … #define RBRQ_END_PDU(rbrq) … #define RBRQ_AAL5_PROT(rbrq) … #define RBRQ_CON_CLOSED(rbrq) … #define RBRQ_HBUF_ERR(rbrq) … #define RBRQ_CID(rbrq) … #define RBRQ_BUFLEN(rbrq) … /* figure 2.3 transmit packet descriptor ready queue */ struct he_tpdrq { … }; #define TPDRQ_ALIGNMENT … /* table 2.30 host status page detail */ #define HSP_ALIGNMENT … struct he_hsp { … }; /* * figure 2.9 receive buffer pools * * since a virtual address might be more than 32 bits, we store an index * in the virt member of he_rbp. NOTE: the lower six bits in the rbrq * addr member are used for buffer status further limiting us to 26 bits. */ struct he_rbp { … }; #define RBP_IDX_OFFSET … /* * the he dma engine will try to hold an extra 16 buffers in its local * caches. and add a couple buffers for safety. */ #define RBPL_TABLE_SIZE … struct he_buff { … }; #ifdef notyet struct he_group { u32 rpbl_size, rpbl_qsize; struct he_rpb_entry *rbpl_ba; }; #endif #define HE_LOOKUP_VCC(dev, cid) … struct he_vcc_table { … }; struct he_cs_stper { … }; #define HE_NUM_CS_STPER … struct he_dev { … }; #define HE_MAXIOV … struct he_vcc { … }; #define HE_VCC(vcc) … #define PCI_VENDOR_ID_FORE … #define PCI_DEVICE_ID_FORE_HE … #define GEN_CNTL_0 … #define INT_PROC_ENBL … #define SLAVE_ENDIAN_MODE … #define MRL_ENB … #define MRM_ENB … #define INIT_ENB … #define IGNORE_TIMEOUT … #define ENBL_64 … #define MIN_PCI_LATENCY … #define HE_DEV(dev) … #define he_is622(dev) … #define he_isMM(dev) … #define HE_REGMAP_SIZE … #define RESET_CNTL … #define BOARD_RST_STATUS … #define HOST_CNTL … #define PCI_BUS_SIZE64 … #define DESC_RD_STATIC_64 … #define DATA_RD_STATIC_64 … #define DATA_WR_STATIC_64 … #define ID_CS … #define ID_WREN … #define ID_DOUT … #define ID_DOFFSET … #define ID_DIN … #define ID_CLOCK … #define QUICK_RD_RETRY … #define QUICK_WR_RETRY … #define OUTFF_ENB … #define CMDFF_ENB … #define PERR_INT_ENB … #define IGNORE_INTR … #define LB_SWAP … #define SWAP_RNUM_MAX(x) … #define DATA_WR_SWAP … #define DESC_RD_SWAP … #define DATA_RD_SWAP … #define INTR_SWAP … #define DESC_WR_SWAP … #define SDRAM_INIT … #define BIG_ENDIAN_HOST … #define XFER_SIZE … #define LB_MEM_ADDR … #define LB_MEM_DATA … #define LB_MEM_ACCESS … #define LB_MEM_HNDSHK … #define LM_MEM_WRITE … #define LM_MEM_READ … #define SDRAM_CTL … #define LB_64_ENB … #define LB_TWR … #define LB_TRP … #define LB_TRAS … #define INT_FIFO … #define INT_MASK_D … #define INT_MASK_C … #define INT_MASK_B … #define INT_MASK_A … #define INT_CLEAR_D … #define INT_CLEAR_C … #define INT_CLEAR_B … #define INT_CLEAR_A … #define ABORT_ADDR … #define IRQ0_BASE … #define IRQ_BASE(x) … #define IRQ_MASK … #define IRQ_TAIL(x) … #define IRQ0_HEAD … #define IRQ_SIZE(x) … #define IRQ_THRESH(x) … #define IRQ_HEAD(x) … /* #define IRQ_PENDING (1) conflict with linux/irq.h */ #define IRQ0_CNTL … #define IRQ_ADDRSEL(x) … #define IRQ_INT_A … #define IRQ_INT_B … #define IRQ_INT_C … #define IRQ_INT_D … #define IRQ_TYPE_ADDR … #define IRQ_TYPE_LINE … #define IRQ0_DATA … #define IRQ1_BASE … #define IRQ1_HEAD … #define IRQ1_CNTL … #define IRQ1_DATA … #define IRQ2_BASE … #define IRQ2_HEAD … #define IRQ2_CNTL … #define IRQ2_DATA … #define IRQ3_BASE … #define IRQ3_HEAD … #define IRQ3_CNTL … #define IRQ3_DATA … #define GRP_10_MAP … #define GRP_32_MAP … #define GRP_54_MAP … #define GRP_76_MAP … #define G0_RBPS_S … #define G0_RBPS_T … #define RBP_TAIL(x) … #define RBP_MASK(x) … #define G0_RBPS_QI … #define RBP_QSIZE(x) … #define RBP_INT_ENB … #define RBP_THRESH(x) … #define G0_RBPS_BS … #define G0_RBPL_S … #define G0_RBPL_T … #define G0_RBPL_QI … #define G0_RBPL_BS … #define G1_RBPS_S … #define G1_RBPS_T … #define G1_RBPS_QI … #define G1_RBPS_BS … #define G1_RBPL_S … #define G1_RBPL_T … #define G1_RBPL_QI … #define G1_RBPL_BS … #define G2_RBPS_S … #define G2_RBPS_T … #define G2_RBPS_QI … #define G2_RBPS_BS … #define G2_RBPL_S … #define G2_RBPL_T … #define G2_RBPL_QI … #define G2_RBPL_BS … #define G3_RBPS_S … #define G3_RBPS_T … #define G3_RBPS_QI … #define G3_RBPS_BS … #define G3_RBPL_S … #define G3_RBPL_T … #define G3_RBPL_QI … #define G3_RBPL_BS … #define G4_RBPS_S … #define G4_RBPS_T … #define G4_RBPS_QI … #define G4_RBPS_BS … #define G4_RBPL_S … #define G4_RBPL_T … #define G4_RBPL_QI … #define G4_RBPL_BS … #define G5_RBPS_S … #define G5_RBPS_T … #define G5_RBPS_QI … #define G5_RBPS_BS … #define G5_RBPL_S … #define G5_RBPL_T … #define G5_RBPL_QI … #define G5_RBPL_BS … #define G6_RBPS_S … #define G6_RBPS_T … #define G6_RBPS_QI … #define G6_RBPS_BS … #define G6_RBPL_S … #define G6_RBPL_T … #define G6_RBPL_QI … #define G6_RBPL_BS … #define G7_RBPS_S … #define G7_RBPS_T … #define G7_RBPS_QI … #define G7_RBPS_BS … #define G7_RBPL_S … #define G7_RBPL_T … #define G7_RBPL_QI … #define G7_RBPL_BS … #define G0_RBRQ_ST … #define G0_RBRQ_H … #define G0_RBRQ_Q … #define RBRQ_THRESH(x) … #define RBRQ_SIZE(x) … #define G0_RBRQ_I … #define RBRQ_TIME(x) … #define RBRQ_COUNT(x) … /* fill in 1 ... 7 later */ #define G0_TBRQ_B_T … #define G0_TBRQ_H … #define G0_TBRQ_S … #define G0_TBRQ_THRESH … #define TBRQ_THRESH(x) … /* fill in 1 ... 7 later */ #define RH_CONFIG … #define PHY_INT_ENB … #define OAM_GID(x) … #define PTMR_PRE(x) … #define G0_INMQ_S … #define G0_INMQ_L … #define G1_INMQ_S … #define G1_INMQ_L … #define G2_INMQ_S … #define G2_INMQ_L … #define G3_INMQ_S … #define G3_INMQ_L … #define G4_INMQ_S … #define G4_INMQ_L … #define G5_INMQ_S … #define G5_INMQ_L … #define G6_INMQ_S … #define G6_INMQ_L … #define G7_INMQ_S … #define G7_INMQ_L … #define TPDRQ_B_H … #define TPDRQ_T … #define TPDRQ_S … #define UBUFF_BA … #define RLBF0_H … #define RLBF0_T … #define RLBF1_H … #define RLBF1_T … #define RLBC_H … #define RLBC_T … #define RLBC_H2 … #define TLBF_H … #define TLBF_T … #define RLBF0_C … #define RLBF1_C … #define RXTHRSH … #define LITHRSH … #define LBARB … #define SLICE_X(x) … #define ARB_RNUM_MAX(x) … #define TH_PRTY(x) … #define RH_PRTY(x) … #define TL_PRTY(x) … #define RL_PRTY(x) … #define BUS_MULTI(x) … #define NET_PREF(x) … #define SDRAMCON … #define BANK_ON … #define WIDE_DATA … #define TWR_WAIT … #define TRP_WAIT … #define TRAS_WAIT … #define REF_RATE(x) … #define LBSTAT … #define RCC_STAT … #define RCC_BUSY … #define TCMCONFIG … #define TM_DESL2 … #define TM_BANK_WAIT(x) … #define TM_ADD_BANK4(x) … #define TM_PAR_CHECK(x) … #define TM_RW_WAIT(x) … #define TM_SRAM_TYPE(x) … #define TSRB_BA … #define TSRC_BA … #define TMABR_BA … #define TPD_BA … #define TSRD_BA … #define TX_CONFIG … #define DRF_THRESH(x) … #define TX_UT_MODE(x) … #define TX_VCI_MASK(x) … #define LBFREE_CNT(x) … #define TXAAL5_PROTO … #define CPCS_UU(x) … #define CPI(x) … #define RCMCONFIG … #define RM_DESL2(x) … #define RM_BANK_WAIT(x) … #define RM_ADD_BANK(x) … #define RM_PAR_CHECK(x) … #define RM_RW_WAIT(x) … #define RM_SRAM_TYPE(x) … #define RCMRSRB_BA … #define RCMLBM_BA … #define RCMABR_BA … #define RC_CONFIG … #define UT_RD_DELAY(x) … #define WRAP_MODE(x) … #define RC_UT_MODE(x) … #define RX_ENABLE … #define RX_VALVP(x) … #define RX_VALVC(x) … #define MCC … #define OEC … #define DCC … #define CEC … #define HSP_BA … #define LB_CONFIG … #define LB_SIZE(x) … #define CON_DAT … #define CON_CTL … #define CON_CTL_MBOX … #define CON_CTL_TCM … #define CON_CTL_RCM … #define CON_CTL_WRITE … #define CON_CTL_READ … #define CON_CTL_BUSY … #define CON_BYTE_DISABLE_3 … #define CON_BYTE_DISABLE_2 … #define CON_BYTE_DISABLE_1 … #define CON_BYTE_DISABLE_0 … #define CON_CTL_ADDR(x) … #define FRAMER … /* 3.3 network controller (internal) mailbox registers */ #define CS_STPER0 … /* ... */ #define CS_STPER31 … #define CS_STTIM0 … /* ... */ #define CS_STTIM31 … #define CS_TGRLD0 … /* ... */ #define CS_TGRLD15 … #define CS_ERTHR0 … #define CS_ERTHR1 … #define CS_ERTHR2 … #define CS_ERTHR3 … #define CS_ERTHR4 … #define CS_ERCTL0 … #define TX_ENABLE … #define ER_ENABLE … #define CS_ERCTL1 … #define CS_ERCTL2 … #define CS_ERSTAT0 … #define CS_ERSTAT1 … #define CS_RTCCT … #define CS_RTFWC … #define CS_RTFWR … #define CS_RTFTC … #define CS_RTATR … #define CS_TFBSET … #define CS_TFBADD … #define CS_TFBSUB … #define CS_WCRMAX … #define CS_WCRMIN … #define CS_WCRINC … #define CS_WCRDEC … #define CS_WCRCEIL … #define CS_BWDCNT … #define CS_OTPPER … #define CS_OTWPER … #define CS_OTTLIM … #define CS_OTTCNT … #define CS_HGRRT0 … /* ... */ #define CS_HGRRT7 … #define CS_ORPTRS … #define RXCON_CLOSE … #define RCM_MEM_SIZE … #define TCM_MEM_SIZE … /* 2.5 transmit connection memory registers */ #define TSR0_CONN_STATE(x) … #define TSR0_USE_WMIN … #define TSR0_GROUP(x) … #define TSR0_ABR … #define TSR0_UBR … #define TSR0_CBR … #define TSR0_PROT … #define TSR0_AAL0_SDU … #define TSR0_AAL0 … #define TSR0_AAL5 … #define TSR0_HALT_ER … #define TSR0_MARK_CI … #define TSR0_MARK_ER … #define TSR0_UPDATE_GER … #define TSR0_RC_INDEX(x) … #define TSR1_PCR(x) … #define TSR1_MCR(x) … #define TSR2_ACR(x) … #define TSR3_NRM_CNT(x) … #define TSR3_CRM_CNT(x) … #define TSR4_FLUSH_CONN … #define TSR4_SESSION_ENDED … #define TSR4_CRC10 … #define TSR4_NULL_CRC10 … #define TSR4_PROT … #define TSR4_AAL0_SDU … #define TSR4_AAL0 … #define TSR4_AAL5 … #define TSR9_OPEN_CONN … #define TSR11_ICR(x) … #define TSR11_TRM(x) … #define TSR11_NRM(x) … #define TSR11_ADTF(x) … #define TSR13_RDF(x) … #define TSR13_RIF(x) … #define TSR13_CDF(x) … #define TSR13_CRM(x) … #define TSR14_DELETE … #define TSR14_ABR_CLOSE … /* 2.7.1 per connection receieve state registers */ #define RSR0_START_PDU … #define RSR0_OPEN_CONN … #define RSR0_CLOSE_CONN … #define RSR0_PPD_ENABLE … #define RSR0_EPD_ENABLE … #define RSR0_TCP_CKSUM … #define RSR0_AAL5 … #define RSR0_AAL0 … #define RSR0_AAL0_SDU … #define RSR0_RAWCELL … #define RSR0_RAWCELL_CRC10 … #define RSR1_AQI_ENABLE … #define RSR1_RBPL_ONLY … #define RSR1_GROUP(x) … #define RSR4_AQI_ENABLE … #define RSR4_GROUP(x) … #define RSR4_RBPL_ONLY … /* 2.1.4 transmit packet descriptor */ #define TPD_USERCELL … #define TPD_SEGMENT_OAMF5 … #define TPD_END2END_OAMF5 … #define TPD_RMCELL … #define TPD_CELLTYPE(x) … #define TPD_EOS … #define TPD_CLP … #define TPD_INT … #define TPD_LST … /* table 4.3 serial eeprom information */ #define PROD_ID … #define PROD_ID_LEN … #define HW_REV … #define M_SN … #define MEDIA … #define HE155MM … #define HE622MM … #define HE155SM … #define HE622SM … #define MAC_ADDR … #define CS_LOW … #define CS_HIGH … #define CLK_LOW … #define CLK_HIGH … #define SI_HIGH … #define EEPROM_DELAY … #endif /* _HE_H_ */
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