/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _FIREWIRE_OHCI_H #define _FIREWIRE_OHCI_H /* OHCI register map */ #define OHCI1394_Version … #define OHCI1394_GUID_ROM … #define OHCI1394_ATRetries … #define OHCI1394_CSRData … #define OHCI1394_CSRCompareData … #define OHCI1394_CSRControl … #define OHCI1394_ConfigROMhdr … #define OHCI1394_BusID … #define OHCI1394_BusOptions … #define OHCI1394_GUIDHi … #define OHCI1394_GUIDLo … #define OHCI1394_ConfigROMmap … #define OHCI1394_PostedWriteAddressLo … #define OHCI1394_PostedWriteAddressHi … #define OHCI1394_VendorID … #define OHCI1394_HCControlSet … #define OHCI1394_HCControlClear … #define OHCI1394_HCControl_BIBimageValid … #define OHCI1394_HCControl_noByteSwapData … #define OHCI1394_HCControl_programPhyEnable … #define OHCI1394_HCControl_aPhyEnhanceEnable … #define OHCI1394_HCControl_LPS … #define OHCI1394_HCControl_postedWriteEnable … #define OHCI1394_HCControl_linkEnable … #define OHCI1394_HCControl_softReset … #define OHCI1394_SelfIDBuffer … #define OHCI1394_SelfIDCount … #define OHCI1394_IRMultiChanMaskHiSet … #define OHCI1394_IRMultiChanMaskHiClear … #define OHCI1394_IRMultiChanMaskLoSet … #define OHCI1394_IRMultiChanMaskLoClear … #define OHCI1394_IntEventSet … #define OHCI1394_IntEventClear … #define OHCI1394_IntMaskSet … #define OHCI1394_IntMaskClear … #define OHCI1394_IsoXmitIntEventSet … #define OHCI1394_IsoXmitIntEventClear … #define OHCI1394_IsoXmitIntMaskSet … #define OHCI1394_IsoXmitIntMaskClear … #define OHCI1394_IsoRecvIntEventSet … #define OHCI1394_IsoRecvIntEventClear … #define OHCI1394_IsoRecvIntMaskSet … #define OHCI1394_IsoRecvIntMaskClear … #define OHCI1394_InitialBandwidthAvailable … #define OHCI1394_InitialChannelsAvailableHi … #define OHCI1394_InitialChannelsAvailableLo … #define OHCI1394_FairnessControl … #define OHCI1394_LinkControlSet … #define OHCI1394_LinkControlClear … #define OHCI1394_LinkControl_rcvSelfID … #define OHCI1394_LinkControl_rcvPhyPkt … #define OHCI1394_LinkControl_cycleTimerEnable … #define OHCI1394_LinkControl_cycleMaster … #define OHCI1394_LinkControl_cycleSource … #define OHCI1394_NodeID … #define OHCI1394_NodeID_idValid … #define OHCI1394_NodeID_root … #define OHCI1394_NodeID_nodeNumber … #define OHCI1394_NodeID_busNumber … #define OHCI1394_PhyControl … #define OHCI1394_PhyControl_Read(addr) … #define OHCI1394_PhyControl_ReadDone … #define OHCI1394_PhyControl_ReadData(r) … #define OHCI1394_PhyControl_Write(addr, data) … #define OHCI1394_PhyControl_WritePending … #define OHCI1394_IsochronousCycleTimer … #define OHCI1394_AsReqFilterHiSet … #define OHCI1394_AsReqFilterHiClear … #define OHCI1394_AsReqFilterLoSet … #define OHCI1394_AsReqFilterLoClear … #define OHCI1394_PhyReqFilterHiSet … #define OHCI1394_PhyReqFilterHiClear … #define OHCI1394_PhyReqFilterLoSet … #define OHCI1394_PhyReqFilterLoClear … #define OHCI1394_PhyUpperBound … #define OHCI1394_AsReqTrContextBase … #define OHCI1394_AsReqTrContextControlSet … #define OHCI1394_AsReqTrContextControlClear … #define OHCI1394_AsReqTrCommandPtr … #define OHCI1394_AsRspTrContextBase … #define OHCI1394_AsRspTrContextControlSet … #define OHCI1394_AsRspTrContextControlClear … #define OHCI1394_AsRspTrCommandPtr … #define OHCI1394_AsReqRcvContextBase … #define OHCI1394_AsReqRcvContextControlSet … #define OHCI1394_AsReqRcvContextControlClear … #define OHCI1394_AsReqRcvCommandPtr … #define OHCI1394_AsRspRcvContextBase … #define OHCI1394_AsRspRcvContextControlSet … #define OHCI1394_AsRspRcvContextControlClear … #define OHCI1394_AsRspRcvCommandPtr … /* Isochronous transmit registers */ #define OHCI1394_IsoXmitContextBase(n) … #define OHCI1394_IsoXmitContextControlSet(n) … #define OHCI1394_IsoXmitContextControlClear(n) … #define OHCI1394_IsoXmitCommandPtr(n) … /* Isochronous receive registers */ #define OHCI1394_IsoRcvContextBase(n) … #define OHCI1394_IsoRcvContextControlSet(n) … #define OHCI1394_IsoRcvContextControlClear(n) … #define OHCI1394_IsoRcvCommandPtr(n) … #define OHCI1394_IsoRcvContextMatch(n) … /* Interrupts Mask/Events */ #define OHCI1394_reqTxComplete … #define OHCI1394_respTxComplete … #define OHCI1394_ARRQ … #define OHCI1394_ARRS … #define OHCI1394_RQPkt … #define OHCI1394_RSPkt … #define OHCI1394_isochTx … #define OHCI1394_isochRx … #define OHCI1394_postedWriteErr … #define OHCI1394_lockRespErr … #define OHCI1394_selfIDComplete … #define OHCI1394_busReset … #define OHCI1394_regAccessFail … #define OHCI1394_phy … #define OHCI1394_cycleSynch … #define OHCI1394_cycle64Seconds … #define OHCI1394_cycleLost … #define OHCI1394_cycleInconsistent … #define OHCI1394_unrecoverableError … #define OHCI1394_cycleTooLong … #define OHCI1394_phyRegRcvd … #define OHCI1394_masterIntEnable … #define OHCI1394_evt_no_status … #define OHCI1394_evt_long_packet … #define OHCI1394_evt_missing_ack … #define OHCI1394_evt_underrun … #define OHCI1394_evt_overrun … #define OHCI1394_evt_descriptor_read … #define OHCI1394_evt_data_read … #define OHCI1394_evt_data_write … #define OHCI1394_evt_bus_reset … #define OHCI1394_evt_timeout … #define OHCI1394_evt_tcode_err … #define OHCI1394_evt_reserved_b … #define OHCI1394_evt_reserved_c … #define OHCI1394_evt_unknown … #define OHCI1394_evt_flushed … #define OHCI1394_phy_tcode … // Self-ID DMA. #define OHCI1394_SelfIDCount_selfIDError_MASK … #define OHCI1394_SelfIDCount_selfIDError_SHIFT … #define OHCI1394_SelfIDCount_selfIDGeneration_MASK … #define OHCI1394_SelfIDCount_selfIDGeneration_SHIFT … #define OHCI1394_SelfIDCount_selfIDSize_MASK … #define OHCI1394_SelfIDCount_selfIDSize_SHIFT … static inline bool ohci1394_self_id_count_is_error(u32 value) { … } static inline u8 ohci1394_self_id_count_get_generation(u32 value) { … } // In 1394 OHCI specification, the maximum size of self ID stream is 504 quadlets // (= 63 devices * 4 self ID packets * 2 quadlets). The selfIDSize field accommodates it and its // additional first quadlet, since the field is 9 bits (0x1ff = 511). static inline u32 ohci1394_self_id_count_get_size(u32 value) { … } #define OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_MASK … #define OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_SHIFT … #define OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_MASK … #define OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_SHIFT … static inline u8 ohci1394_self_id_receive_q0_get_generation(u32 quadlet0) { … } static inline u16 ohci1394_self_id_receive_q0_get_timestamp(u32 quadlet0) { … } #endif /* _FIREWIRE_OHCI_H */
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