/* SPDX-License-Identifier: GPL-2.0 */ /* * Chip register definitions for PCILynx chipset. Based on pcilynx.h * from the Linux 1394 drivers, but modified a bit so the names here * match the specification exactly (even though they have weird names, * like xxx_OVER_FLOW, or arbitrary abbreviations like SNTRJ for "sent * reject" etc.) */ #define PCILYNX_MAX_REGISTER … #define PCILYNX_MAX_MEMORY … #define PCI_LATENCY_CACHELINE … #define MISC_CONTROL … #define MISC_CONTROL_SWRESET … #define SERIAL_EEPROM_CONTROL … #define PCI_INT_STATUS … #define PCI_INT_ENABLE … /* status and enable have identical bit numbers */ #define PCI_INT_INT_PEND … #define PCI_INT_FRC_INT … #define PCI_INT_SLV_ADR_PERR … #define PCI_INT_SLV_DAT_PERR … #define PCI_INT_MST_DAT_PERR … #define PCI_INT_MST_DEV_TO … #define PCI_INT_INT_SLV_TO … #define PCI_INT_AUX_TO … #define PCI_INT_AUX_INT … #define PCI_INT_P1394_INT … #define PCI_INT_DMA4_PCL … #define PCI_INT_DMA4_HLT … #define PCI_INT_DMA3_PCL … #define PCI_INT_DMA3_HLT … #define PCI_INT_DMA2_PCL … #define PCI_INT_DMA2_HLT … #define PCI_INT_DMA1_PCL … #define PCI_INT_DMA1_HLT … #define PCI_INT_DMA0_PCL … #define PCI_INT_DMA0_HLT … /* all DMA interrupts combined: */ #define PCI_INT_DMA_ALL … #define PCI_INT_DMA_HLT(chan) … #define PCI_INT_DMA_PCL(chan) … #define LBUS_ADDR … #define LBUS_ADDR_SEL_RAM … #define LBUS_ADDR_SEL_ROM … #define LBUS_ADDR_SEL_AUX … #define LBUS_ADDR_SEL_ZV … #define GPIO_CTRL_A … #define GPIO_CTRL_B … #define GPIO_DATA_BASE … #define DMA_BREG(base, chan) … #define DMA_SREG(base, chan) … #define PCL_NEXT_INVALID … /* transfer commands */ #define PCL_CMD_RCV … #define PCL_CMD_RCV_AND_UPDATE … #define PCL_CMD_XMT … #define PCL_CMD_UNFXMT … #define PCL_CMD_PCI_TO_LBUS … #define PCL_CMD_LBUS_TO_PCI … /* aux commands */ #define PCL_CMD_NOP … #define PCL_CMD_LOAD … #define PCL_CMD_STOREQ … #define PCL_CMD_STORED … #define PCL_CMD_STORE0 … #define PCL_CMD_STORE1 … #define PCL_CMD_COMPARE … #define PCL_CMD_SWAP_COMPARE … #define PCL_CMD_ADD … #define PCL_CMD_BRANCH … /* BRANCH condition codes */ #define PCL_COND_DMARDY_SET … #define PCL_COND_DMARDY_CLEAR … #define PCL_GEN_INTR … #define PCL_LAST_BUFF … #define PCL_LAST_CMD … #define PCL_WAITSTAT … #define PCL_BIGENDIAN … #define PCL_ISOMODE … #define DMA0_PREV_PCL … #define DMA1_PREV_PCL … #define DMA2_PREV_PCL … #define DMA3_PREV_PCL … #define DMA4_PREV_PCL … #define DMA_PREV_PCL(chan) … #define DMA0_CURRENT_PCL … #define DMA1_CURRENT_PCL … #define DMA2_CURRENT_PCL … #define DMA3_CURRENT_PCL … #define DMA4_CURRENT_PCL … #define DMA_CURRENT_PCL(chan) … #define DMA0_CHAN_STAT … #define DMA1_CHAN_STAT … #define DMA2_CHAN_STAT … #define DMA3_CHAN_STAT … #define DMA4_CHAN_STAT … #define DMA_CHAN_STAT(chan) … /* CHAN_STATUS registers share bits */ #define DMA_CHAN_STAT_SELFID … #define DMA_CHAN_STAT_ISOPKT … #define DMA_CHAN_STAT_PCIERR … #define DMA_CHAN_STAT_PKTERR … #define DMA_CHAN_STAT_PKTCMPL … #define DMA_CHAN_STAT_SPECIALACK … #define DMA0_CHAN_CTRL … #define DMA1_CHAN_CTRL … #define DMA2_CHAN_CTRL … #define DMA3_CHAN_CTRL … #define DMA4_CHAN_CTRL … #define DMA_CHAN_CTRL(chan) … /* CHAN_CTRL registers share bits */ #define DMA_CHAN_CTRL_ENABLE … #define DMA_CHAN_CTRL_BUSY … #define DMA_CHAN_CTRL_LINK … #define DMA0_READY … #define DMA1_READY … #define DMA2_READY … #define DMA3_READY … #define DMA4_READY … #define DMA_READY(chan) … #define DMA_GLOBAL_REGISTER … #define FIFO_SIZES … #define FIFO_CONTROL … #define FIFO_CONTROL_GRF_FLUSH … #define FIFO_CONTROL_ITF_FLUSH … #define FIFO_CONTROL_ATF_FLUSH … #define FIFO_XMIT_THRESHOLD … #define DMA0_WORD0_CMP_VALUE … #define DMA1_WORD0_CMP_VALUE … #define DMA2_WORD0_CMP_VALUE … #define DMA3_WORD0_CMP_VALUE … #define DMA4_WORD0_CMP_VALUE … #define DMA_WORD0_CMP_VALUE(chan) … #define DMA0_WORD0_CMP_ENABLE … #define DMA1_WORD0_CMP_ENABLE … #define DMA2_WORD0_CMP_ENABLE … #define DMA3_WORD0_CMP_ENABLE … #define DMA4_WORD0_CMP_ENABLE … #define DMA_WORD0_CMP_ENABLE(chan) … #define DMA0_WORD1_CMP_VALUE … #define DMA1_WORD1_CMP_VALUE … #define DMA2_WORD1_CMP_VALUE … #define DMA3_WORD1_CMP_VALUE … #define DMA4_WORD1_CMP_VALUE … #define DMA_WORD1_CMP_VALUE(chan) … #define DMA0_WORD1_CMP_ENABLE … #define DMA1_WORD1_CMP_ENABLE … #define DMA2_WORD1_CMP_ENABLE … #define DMA3_WORD1_CMP_ENABLE … #define DMA4_WORD1_CMP_ENABLE … #define DMA_WORD1_CMP_ENABLE(chan) … /* word 1 compare enable flags */ #define DMA_WORD1_CMP_MATCH_OTHERBUS … #define DMA_WORD1_CMP_MATCH_BROADCAST … #define DMA_WORD1_CMP_MATCH_BUS_BCAST … #define DMA_WORD1_CMP_MATCH_LOCAL_NODE … #define DMA_WORD1_CMP_MATCH_EXACT … #define DMA_WORD1_CMP_ENABLE_SELF_ID … #define DMA_WORD1_CMP_ENABLE_MASTER … #define LINK_ID … #define LINK_ID_BUS(id) … #define LINK_ID_NODE(id) … #define LINK_CONTROL … #define LINK_CONTROL_BUSY … #define LINK_CONTROL_TX_ISO_EN … #define LINK_CONTROL_RX_ISO_EN … #define LINK_CONTROL_TX_ASYNC_EN … #define LINK_CONTROL_RX_ASYNC_EN … #define LINK_CONTROL_RESET_TX … #define LINK_CONTROL_RESET_RX … #define LINK_CONTROL_CYCMASTER … #define LINK_CONTROL_CYCSOURCE … #define LINK_CONTROL_CYCTIMEREN … #define LINK_CONTROL_RCV_CMP_VALID … #define LINK_CONTROL_SNOOP_ENABLE … #define CYCLE_TIMER … #define LINK_PHY … #define LINK_PHY_READ … #define LINK_PHY_WRITE … #define LINK_PHY_ADDR(addr) … #define LINK_PHY_WDATA(data) … #define LINK_PHY_RADDR(addr) … #define LINK_INT_STATUS … #define LINK_INT_ENABLE … /* status and enable have identical bit numbers */ #define LINK_INT_LINK_INT … #define LINK_INT_PHY_TIME_OUT … #define LINK_INT_PHY_REG_RCVD … #define LINK_INT_PHY_BUSRESET … #define LINK_INT_TX_RDY … #define LINK_INT_RX_DATA_RDY … #define LINK_INT_IT_STUCK … #define LINK_INT_AT_STUCK … #define LINK_INT_SNTRJ … #define LINK_INT_HDR_ERR … #define LINK_INT_TC_ERR … #define LINK_INT_CYC_SEC … #define LINK_INT_CYC_STRT … #define LINK_INT_CYC_DONE … #define LINK_INT_CYC_PEND … #define LINK_INT_CYC_LOST … #define LINK_INT_CYC_ARB_FAILED … #define LINK_INT_GRF_OVER_FLOW … #define LINK_INT_ITF_UNDER_FLOW … #define LINK_INT_ATF_UNDER_FLOW … #define LINK_INT_IARB_FAILED …
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