// SPDX-License-Identifier: GPL-2.0-or-later /* * init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers * * Copyright (C) 2006-2007 Bernhard Kaindl <[email protected]> * * Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c * this file has functions to: * - scan the PCI very early on boot for all OHCI 1394-compliant controllers * - reset and initialize them and make them join the IEEE1394 bus and * - enable physical DMA on them to allow remote debugging * * All code and data is marked as __init and __initdata, respective as * during boot, all OHCI1394 controllers may be claimed by the firewire * stack and at this point, this code should not touch them anymore. * * To use physical DMA after the initialization of the firewire stack, * be sure that the stack enables it and (re-)attach after the bus reset * which may be caused by the firewire stack initialization. */ #include <linux/delay.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/pci.h> /* for PCI defines */ #include <linux/string.h> #include <asm/pci-direct.h> /* for direct PCI config space access */ #include <asm/fixmap.h> #include <linux/init_ohci1394_dma.h> #include "ohci.h" int __initdata init_ohci1394_dma_early; struct ohci { … }; static inline void reg_write(const struct ohci *ohci, int offset, u32 data) { … } static inline u32 reg_read(const struct ohci *ohci, int offset) { … } #define OHCI_LOOP_COUNT … /* Reads a PHY register of an OHCI-1394 controller */ static inline u8 __init get_phy_reg(struct ohci *ohci, u8 addr) { … } /* Writes to a PHY register of an OHCI-1394 controller */ static inline void __init set_phy_reg(struct ohci *ohci, u8 addr, u8 data) { … } /* Resets an OHCI-1394 controller (for sane state before initialization) */ static inline void __init init_ohci1394_soft_reset(struct ohci *ohci) { … } #define OHCI1394_MAX_AT_REQ_RETRIES … #define OHCI1394_MAX_AT_RESP_RETRIES … #define OHCI1394_MAX_PHYS_RESP_RETRIES … /* Basic OHCI-1394 register and port inititalization */ static inline void __init init_ohci1394_initialize(struct ohci *ohci) { … } /** * init_ohci1394_wait_for_busresets - wait until bus resets are completed * * OHCI1394 initialization itself and any device going on- or offline * and any cable issue cause a IEEE1394 bus reset. The OHCI1394 spec * specifies that physical DMA is disabled on each bus reset and it * has to be enabled after each bus reset when needed. We resort * to polling here because on early boot, we have no interrupts. */ static inline void __init init_ohci1394_wait_for_busresets(struct ohci *ohci) { … } /** * init_ohci1394_enable_physical_dma - Enable physical DMA for remote debugging * This enables remote DMA access over IEEE1394 from every host for the low * 4GB of address space. DMA accesses above 4GB are not available currently. */ static inline void __init init_ohci1394_enable_physical_dma(struct ohci *ohci) { … } /** * init_ohci1394_reset_and_init_dma - init controller and enable DMA * This initializes the given controller and enables physical DMA engine in it. */ static inline void __init init_ohci1394_reset_and_init_dma(struct ohci *ohci) { … } /** * init_ohci1394_controller - Map the registers of the controller and init DMA * This maps the registers of the specified controller and initializes it */ static inline void __init init_ohci1394_controller(int num, int slot, int func) { … } /** * init_ohci1394_dma_on_all_controllers - scan for OHCI1394 controllers and init DMA on them * Scans the whole PCI space for OHCI1394 controllers and inits DMA on them */ void __init init_ohci1394_dma_on_all_controllers(void) { … } /** * setup_ohci1394_dma - enables early OHCI1394 DMA initialization */ static int __init setup_ohci1394_dma(char *opt) { … } /* passing ohci1394_dma=early on boot causes early OHCI1394 DMA initialization */ early_param(…);
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