/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2019 HiSilicon Limited. */ #ifndef HISI_ACC_QM_H #define HISI_ACC_QM_H #include <linux/bitfield.h> #include <linux/debugfs.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/pci.h> #define QM_QNUM_V1 … #define QM_QNUM_V2 … #define QM_MAX_VFS_NUM_V2 … /* qm user domain */ #define QM_ARUSER_M_CFG_1 … #define AXUSER_SNOOP_ENABLE … #define AXUSER_CMD_TYPE … #define AXUSER_CMD_SMMU_NORMAL … #define AXUSER_NS … #define AXUSER_NO … #define AXUSER_FP … #define AXUSER_SSV … #define AXUSER_BASE … #define QM_ARUSER_M_CFG_ENABLE … #define ARUSER_M_CFG_ENABLE … #define QM_AWUSER_M_CFG_1 … #define QM_AWUSER_M_CFG_ENABLE … #define AWUSER_M_CFG_ENABLE … #define QM_WUSER_M_CFG_ENABLE … #define WUSER_M_CFG_ENABLE … /* mailbox */ #define QM_MB_CMD_SQC … #define QM_MB_CMD_CQC … #define QM_MB_CMD_EQC … #define QM_MB_CMD_AEQC … #define QM_MB_CMD_SQC_BT … #define QM_MB_CMD_CQC_BT … #define QM_MB_CMD_SQC_VFT_V2 … #define QM_MB_CMD_STOP_QP … #define QM_MB_CMD_FLUSH_QM … #define QM_MB_CMD_SRC … #define QM_MB_CMD_DST … #define QM_MB_CMD_SEND_BASE … #define QM_MB_EVENT_SHIFT … #define QM_MB_BUSY_SHIFT … #define QM_MB_OP_SHIFT … #define QM_MB_CMD_DATA_ADDR_L … #define QM_MB_CMD_DATA_ADDR_H … #define QM_MB_MAX_WAIT_CNT … /* doorbell */ #define QM_DOORBELL_CMD_SQ … #define QM_DOORBELL_CMD_CQ … #define QM_DOORBELL_CMD_EQ … #define QM_DOORBELL_CMD_AEQ … #define QM_DOORBELL_SQ_CQ_BASE_V2 … #define QM_DOORBELL_EQ_AEQ_BASE_V2 … #define QM_QP_MAX_NUM_SHIFT … #define QM_DB_CMD_SHIFT_V2 … #define QM_DB_RAND_SHIFT_V2 … #define QM_DB_INDEX_SHIFT_V2 … #define QM_DB_PRIORITY_SHIFT_V2 … #define QM_VF_STATE … /* qm cache */ #define QM_CACHE_CTL … #define SQC_CACHE_ENABLE … #define CQC_CACHE_ENABLE … #define SQC_CACHE_WB_ENABLE … #define SQC_CACHE_WB_THRD … #define CQC_CACHE_WB_ENABLE … #define CQC_CACHE_WB_THRD … #define QM_AXI_M_CFG … #define AXI_M_CFG … #define QM_AXI_M_CFG_ENABLE … #define AM_CFG_SINGLE_PORT_MAX_TRANS … #define AXI_M_CFG_ENABLE … #define QM_PEH_AXUSER_CFG … #define QM_PEH_AXUSER_CFG_ENABLE … #define PEH_AXUSER_CFG … #define PEH_AXUSER_CFG_ENABLE … #define QM_MIN_QNUM … #define HISI_ACC_SGL_SGE_NR_MAX … #define QM_SHAPER_CFG … #define QM_SHAPER_ENABLE … #define QM_SHAPER_TYPE1_OFFSET … /* page number for queue file region */ #define QM_DOORBELL_PAGE_NR … /* uacce mode of the driver */ #define UACCE_MODE_NOUACCE … #define UACCE_MODE_SVA … #define UACCE_MODE_DESC … enum qm_stop_reason { … }; enum qm_state { … }; enum qp_state { … }; enum qm_hw_ver { … }; enum qm_fun_type { … }; enum qm_debug_file { … }; enum qm_vf_state { … }; enum qm_misc_ctl_bits { … }; enum qm_cap_bits { … }; struct qm_dev_alg { … }; struct qm_dev_dfx { … }; struct dfx_diff_registers { … }; struct qm_dfx { … }; struct debugfs_file { … }; struct qm_debug { … }; struct qm_shaper_factor { … }; struct qm_dma { … }; struct hisi_qm_status { … }; struct hisi_qm; struct hisi_qm_err_info { … }; struct hisi_qm_err_status { … }; struct hisi_qm_err_ini { … }; struct hisi_qm_cap_info { … }; struct hisi_qm_cap_record { … }; struct hisi_qm_cap_tables { … }; struct hisi_qm_list { … }; struct hisi_qm_poll_data { … }; /** * struct qm_err_isolate * @isolate_lock: protects device error log * @err_threshold: user config error threshold which triggers isolation * @is_isolate: device isolation state * @uacce_hw_errs: index into qm device error list */ struct qm_err_isolate { … }; struct qm_rsv_buf { … }; struct hisi_qm { … }; struct hisi_qp_status { … }; struct hisi_qp_ops { … }; struct hisi_qp { … }; static inline int q_num_set(const char *val, const struct kernel_param *kp, unsigned int device) { … } static inline int vfs_num_set(const char *val, const struct kernel_param *kp) { … } static inline int mode_set(const char *val, const struct kernel_param *kp) { … } static inline int uacce_mode_set(const char *val, const struct kernel_param *kp) { … } static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list) { … } static inline void hisi_qm_add_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list) { … } static inline void hisi_qm_del_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list) { … } int hisi_qm_init(struct hisi_qm *qm); void hisi_qm_uninit(struct hisi_qm *qm); int hisi_qm_start(struct hisi_qm *qm); int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r); int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg); void hisi_qm_stop_qp(struct hisi_qp *qp); int hisi_qp_send(struct hisi_qp *qp, const void *msg); void hisi_qm_debug_init(struct hisi_qm *qm); void hisi_qm_debug_regs_clear(struct hisi_qm *qm); int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs); int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen); int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs); void hisi_qm_dev_err_init(struct hisi_qm *qm); void hisi_qm_dev_err_uninit(struct hisi_qm *qm); int hisi_qm_regs_debugfs_init(struct hisi_qm *qm, struct dfx_diff_registers *dregs, u32 reg_len); void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len); void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s, struct dfx_diff_registers *dregs, u32 regs_len); pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev, pci_channel_state_t state); pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev); void hisi_qm_reset_prepare(struct pci_dev *pdev); void hisi_qm_reset_done(struct pci_dev *pdev); int hisi_qm_wait_mb_ready(struct hisi_qm *qm); int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue, bool op); struct hisi_acc_sgl_pool; struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev, struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool, u32 index, dma_addr_t *hw_sgl_dma); void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl, struct hisi_acc_hw_sgl *hw_sgl); struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev, u32 count, u32 sge_nr); void hisi_acc_free_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool); int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num, u8 alg_type, int node, struct hisi_qp **qps); void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num); void hisi_qm_dev_shutdown(struct pci_dev *pdev); void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list); int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard); void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard); int hisi_qm_resume(struct device *dev); int hisi_qm_suspend(struct device *dev); void hisi_qm_pm_uninit(struct hisi_qm *qm); void hisi_qm_pm_init(struct hisi_qm *qm); int hisi_qm_get_dfx_access(struct hisi_qm *qm); void hisi_qm_put_dfx_access(struct hisi_qm *qm); void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset); u32 hisi_qm_get_hw_info(struct hisi_qm *qm, const struct hisi_qm_cap_info *info_table, u32 index, bool is_read); int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs, u32 dev_algs_size); /* Used by VFIO ACC live migration driver */ struct pci_driver *hisi_sec_get_pf_driver(void); struct pci_driver *hisi_hpre_get_pf_driver(void); struct pci_driver *hisi_zip_get_pf_driver(void); #endif
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