/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Geode LX framebuffer driver * * Copyright (C) 2006-2007, Advanced Micro Devices,Inc. * Copyright (c) 2008 Andres Salomon <[email protected]> */ #ifndef _LXFB_H_ #define _LXFB_H_ #include <linux/fb.h> #define GP_REG_COUNT … #define DC_REG_COUNT … #define VP_REG_COUNT … #define FP_REG_COUNT … #define DC_PAL_COUNT … #define DC_HFILT_COUNT … #define DC_VFILT_COUNT … #define VP_COEFF_SIZE … #define VP_PAL_COUNT … #define OUTPUT_CRT … #define OUTPUT_PANEL … struct lxfb_par { … }; static inline unsigned int lx_get_pitch(unsigned int xres, int bpp) { … } void lx_set_mode(struct fb_info *); unsigned int lx_framebuffer_size(void); int lx_blank_display(struct fb_info *, int); void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int, unsigned int, unsigned int); int lx_powerdown(struct fb_info *info); int lx_powerup(struct fb_info *info); /* Graphics Processor registers (table 6-29 from the data book) */ enum gp_registers { … }; #define GP_BLT_STATUS_CE … #define GP_BLT_STATUS_PB … /* Display Controller registers (table 6-47 from the data book) */ enum dc_registers { … }; #define DC_UNLOCK_LOCK … #define DC_UNLOCK_UNLOCK … #define DC_GENERAL_CFG_FDTY … #define DC_GENERAL_CFG_DFHPEL_SHIFT … #define DC_GENERAL_CFG_DFHPSL_SHIFT … #define DC_GENERAL_CFG_VGAE … #define DC_GENERAL_CFG_DECE … #define DC_GENERAL_CFG_CMPE … #define DC_GENERAL_CFG_VIDE … #define DC_GENERAL_CFG_DFLE … #define DC_DISPLAY_CFG_VISL … #define DC_DISPLAY_CFG_PALB … #define DC_DISPLAY_CFG_DCEN … #define DC_DISPLAY_CFG_DISP_MODE_24BPP … #define DC_DISPLAY_CFG_DISP_MODE_16BPP … #define DC_DISPLAY_CFG_DISP_MODE_8BPP … #define DC_DISPLAY_CFG_TRUP … #define DC_DISPLAY_CFG_VDEN … #define DC_DISPLAY_CFG_GDEN … #define DC_DISPLAY_CFG_TGEN … #define DC_DV_TOP_DV_TOP_EN … #define DC_DV_CTL_DV_LINE_SIZE … #define DC_DV_CTL_DV_LINE_SIZE_1K … #define DC_DV_CTL_DV_LINE_SIZE_2K … #define DC_DV_CTL_DV_LINE_SIZE_4K … #define DC_DV_CTL_DV_LINE_SIZE_8K … #define DC_DV_CTL_CLEAR_DV_RAM … #define DC_IRQ_FILT_CTL_H_FILT_SEL … #define DC_CLR_KEY_CLR_KEY_EN … #define DC_IRQ_VIP_VSYNC_IRQ_STATUS … #define DC_IRQ_STATUS … #define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK … #define DC_IRQ_MASK … #define DC_GENLK_CTL_FLICK_SEL_MASK … #define DC_GENLK_CTL_ALPHA_FLICK_EN … #define DC_GENLK_CTL_FLICK_EN … #define DC_GENLK_CTL_GENLK_EN … /* * Video Processor registers (table 6-71). * There is space for 64 bit values, but we never use more than the * lower 32 bits. The actual register save/restore code only bothers * to restore those 32 bits. */ enum vp_registers { … }; #define VP_VCFG_VID_EN … #define VP_DCFG_GV_GAM … #define VP_DCFG_PWR_SEQ_DELAY … #define VP_DCFG_PWR_SEQ_DELAY_DEFAULT … #define VP_DCFG_CRT_SYNC_SKW … #define VP_DCFG_CRT_SYNC_SKW_DEFAULT … #define VP_DCFG_CRT_VSYNC_POL … #define VP_DCFG_CRT_HSYNC_POL … #define VP_DCFG_DAC_BL_EN … #define VP_DCFG_VSYNC_EN … #define VP_DCFG_HSYNC_EN … #define VP_DCFG_CRT_EN … #define VP_MISC_APWRDN … #define VP_MISC_DACPWRDN … #define VP_MISC_BYP_BOTH … /* * Flat Panel registers (table 6-71). * Also 64 bit registers; see above note about 32-bit handling. */ /* we're actually in the VP register space, starting at address 0x400 */ #define VP_FP_START … enum fp_registers { … }; #define FP_PT2_HSP … #define FP_PT2_VSP … #define FP_PT2_SCRC … #define FP_PM_P … #define FP_PM_PANEL_PWR_UP … #define FP_PM_PANEL_PWR_DOWN … #define FP_PM_PANEL_OFF … #define FP_PM_PANEL_ON … #define FP_DFC_BC … /* register access functions */ static inline uint32_t read_gp(struct lxfb_par *par, int reg) { … } static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val) { … } static inline uint32_t read_dc(struct lxfb_par *par, int reg) { … } static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val) { … } static inline uint32_t read_vp(struct lxfb_par *par, int reg) { … } static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val) { … } static inline uint32_t read_fp(struct lxfb_par *par, int reg) { … } static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val) { … } /* MSRs are defined in linux/cs5535.h; their bitfields are here */ #define MSR_GLCP_DOTPLL_LOCK … #define MSR_GLCP_DOTPLL_HALFPIX … #define MSR_GLCP_DOTPLL_BYPASS … #define MSR_GLCP_DOTPLL_DOTRESET … /* note: this is actually the VP's GLD_MSR_CONFIG */ #define MSR_LX_GLD_MSR_CONFIG_FMT … #define MSR_LX_GLD_MSR_CONFIG_FMT_FP … #define MSR_LX_GLD_MSR_CONFIG_FMT_CRT … #define MSR_LX_GLD_MSR_CONFIG_FPC … #define MSR_LX_MSR_PADSEL_TFT_SEL_LOW … #define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH … #define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO … #define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL … #define MSR_LX_SPARE_MSR_WM_LPEN_OVRD … #define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M … #define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI … #define MSR_LX_SPARE_MSR_DIS_VIFO_WM … #define MSR_LX_SPARE_MSR_DIS_CWD_CHECK … #define MSR_LX_SPARE_MSR_PIX8_PAN_FIX … #define MSR_LX_SPARE_MSR_FIRST_REQ_MASK … #endif
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