/* * i82365.h 1.15 1999/10/25 20:03:34 * * The contents of this file are subject to the Mozilla Public License * Version 1.1 (the "License"); you may not use this file except in * compliance with the License. You may obtain a copy of the License * at http://www.mozilla.org/MPL/ * * Software distributed under the License is distributed on an "AS IS" * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See * the License for the specific language governing rights and * limitations under the License. * * The initial developer of the original code is David A. Hinds * <[email protected]>. Portions created by David A. Hinds * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. * * Alternatively, the contents of this file may be used under the * terms of the GNU General Public License version 2 (the "GPL"), in which * case the provisions of the GPL are applicable instead of the * above. If you wish to allow the use of your version of this file * only under the terms of the GPL and not to allow others to use * your version of this file under the MPL, indicate your decision by * deleting the provisions above and replace them with the notice and * other provisions required by the GPL. If you do not delete the * provisions above, a recipient may use your version of this file * under either the MPL or the GPL. */ #ifndef _LINUX_I82365_H #define _LINUX_I82365_H /* register definitions for the Intel 82365SL PCMCIA controller */ /* Offsets for PCIC registers */ #define I365_IDENT … #define I365_STATUS … #define I365_POWER … #define I365_INTCTL … #define I365_CSC … #define I365_CSCINT … #define I365_ADDRWIN … #define I365_IOCTL … #define I365_GENCTL … #define I365_GBLCTL … /* Offsets for I/O and memory window registers */ #define I365_IO(map) … #define I365_MEM(map) … #define I365_W_START … #define I365_W_STOP … #define I365_W_OFF … /* Flags for I365_STATUS */ #define I365_CS_BVD1 … #define I365_CS_STSCHG … #define I365_CS_BVD2 … #define I365_CS_SPKR … #define I365_CS_DETECT … #define I365_CS_WRPROT … #define I365_CS_READY … #define I365_CS_POWERON … #define I365_CS_GPI … /* Flags for I365_POWER */ #define I365_PWR_OFF … #define I365_PWR_OUT … #define I365_PWR_NORESET … #define I365_PWR_AUTO … #define I365_VCC_MASK … /* There are different layouts for B-step and DF-step chips: the B step has independent Vpp1/Vpp2 control, and the DF step has only Vpp1 control, plus 3V control */ #define I365_VCC_5V … #define I365_VCC_3V … #define I365_VPP2_MASK … #define I365_VPP2_5V … #define I365_VPP2_12V … #define I365_VPP1_MASK … #define I365_VPP1_5V … #define I365_VPP1_12V … /* Flags for I365_INTCTL */ #define I365_RING_ENA … #define I365_PC_RESET … #define I365_PC_IOCARD … #define I365_INTR_ENA … #define I365_IRQ_MASK … /* Flags for I365_CSC and I365_CSCINT*/ #define I365_CSC_BVD1 … #define I365_CSC_STSCHG … #define I365_CSC_BVD2 … #define I365_CSC_READY … #define I365_CSC_DETECT … #define I365_CSC_ANY … #define I365_CSC_GPI … #define I365_CSC_IRQ_MASK … /* Flags for I365_ADDRWIN */ #define I365_ENA_IO(map) … #define I365_ENA_MEM(map) … /* Flags for I365_IOCTL */ #define I365_IOCTL_MASK(map) … #define I365_IOCTL_WAIT(map) … #define I365_IOCTL_0WS(map) … #define I365_IOCTL_IOCS16(map) … #define I365_IOCTL_16BIT(map) … /* Flags for I365_GENCTL */ #define I365_CTL_16DELAY … #define I365_CTL_RESET … #define I365_CTL_GPI_ENA … #define I365_CTL_GPI_CTL … #define I365_CTL_RESUME … #define I365_CTL_SW_IRQ … /* Flags for I365_GBLCTL */ #define I365_GBL_PWRDOWN … #define I365_GBL_CSC_LEV … #define I365_GBL_WRBACK … #define I365_GBL_IRQ_0_LEV … #define I365_GBL_IRQ_1_LEV … /* Flags for memory window registers */ #define I365_MEM_16BIT … #define I365_MEM_0WS … #define I365_MEM_WS1 … #define I365_MEM_WS0 … #define I365_MEM_WRPROT … #define I365_MEM_REG … #define I365_REG(slot, reg) … #endif /* _LINUX_I82365_H */
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