/* * cirrus.h 1.4 1999/10/25 20:03:34 * * The contents of this file are subject to the Mozilla Public License * Version 1.1 (the "License"); you may not use this file except in * compliance with the License. You may obtain a copy of the License * at http://www.mozilla.org/MPL/ * * Software distributed under the License is distributed on an "AS IS" * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See * the License for the specific language governing rights and * limitations under the License. * * The initial developer of the original code is David A. Hinds * <[email protected]>. Portions created by David A. Hinds * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. * * Alternatively, the contents of this file may be used under the * terms of the GNU General Public License version 2 (the "GPL"), in which * case the provisions of the GPL are applicable instead of the * above. If you wish to allow the use of your version of this file * only under the terms of the GPL and not to allow others to use * your version of this file under the MPL, indicate your decision by * deleting the provisions above and replace them with the notice and * other provisions required by the GPL. If you do not delete the * provisions above, a recipient may use your version of this file * under either the MPL or the GPL. */ #ifndef _LINUX_CIRRUS_H #define _LINUX_CIRRUS_H #define PD67_MISC_CTL_1 … #define PD67_FIFO_CTL … #define PD67_MISC_CTL_2 … #define PD67_CHIP_INFO … #define PD67_ATA_CTL … #define PD67_EXT_INDEX … #define PD67_EXT_DATA … /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */ #define PD67_DATA_MASK0 … #define PD67_DATA_MASK1 … #define PD67_DMA_CTL … /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */ #define PD67_EXT_CTL_1 … #define PD67_MEM_PAGE(n) … #define PD67_EXTERN_DATA … #define PD67_MISC_CTL_3 … #define PD67_SMB_PWR_CTL … /* I/O window address offset */ #define PD67_IO_OFF(w) … /* Timing register sets */ #define PD67_TIME_SETUP(n) … #define PD67_TIME_CMD(n) … #define PD67_TIME_RECOV(n) … /* Flags for PD67_MISC_CTL_1 */ #define PD67_MC1_5V_DET … #define PD67_MC1_MEDIA_ENA … #define PD67_MC1_VCC_3V … #define PD67_MC1_PULSE_MGMT … #define PD67_MC1_PULSE_IRQ … #define PD67_MC1_SPKR_ENA … #define PD67_MC1_INPACK_ENA … /* Flags for PD67_FIFO_CTL */ #define PD67_FIFO_EMPTY … /* Flags for PD67_MISC_CTL_2 */ #define PD67_MC2_FREQ_BYPASS … #define PD67_MC2_DYNAMIC_MODE … #define PD67_MC2_SUSPEND … #define PD67_MC2_5V_CORE … #define PD67_MC2_LED_ENA … #define PD67_MC2_FAST_PCI … #define PD67_MC2_3STATE_BIT7 … #define PD67_MC2_DMA_MODE … #define PD67_MC2_IRQ15_RI … /* Flags for PD67_CHIP_INFO */ #define PD67_INFO_SLOTS … #define PD67_INFO_CHIP_ID … #define PD67_INFO_REV … /* Fields in PD67_TIME_* registers */ #define PD67_TIME_SCALE … #define PD67_TIME_SCALE_1 … #define PD67_TIME_SCALE_16 … #define PD67_TIME_SCALE_256 … #define PD67_TIME_SCALE_4096 … #define PD67_TIME_MULT … /* Fields in PD67_DMA_CTL */ #define PD67_DMA_MODE … #define PD67_DMA_OFF … #define PD67_DMA_DREQ_INPACK … #define PD67_DMA_DREQ_WP … #define PD67_DMA_DREQ_BVD2 … #define PD67_DMA_PULLUP … /* Fields in PD67_EXT_CTL_1 */ #define PD67_EC1_VCC_PWR_LOCK … #define PD67_EC1_AUTO_PWR_CLEAR … #define PD67_EC1_LED_ENA … #define PD67_EC1_INV_CARD_IRQ … #define PD67_EC1_INV_MGMT_IRQ … #define PD67_EC1_PULLUP_CTL … /* Fields in PD67_MISC_CTL_3 */ #define PD67_MC3_IRQ_MASK … #define PD67_MC3_IRQ_PCPCI … #define PD67_MC3_IRQ_EXTERN … #define PD67_MC3_IRQ_PCIWAY … #define PD67_MC3_IRQ_PCI … #define PD67_MC3_PWR_MASK … #define PD67_MC3_PWR_SERIAL … #define PD67_MC3_PWR_TI2202 … #define PD67_MC3_PWR_SMB … /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */ /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */ #define PD68_EXT_CTL_2 … #define PD68_PCI_SPACE … #define PD68_PCCARD_SPACE … #define PD68_WINDOW_TYPE … #define PD68_EXT_CSC … #define PD68_MISC_CTL_4 … #define PD68_MISC_CTL_5 … #define PD68_MISC_CTL_6 … /* Extra flags in PD67_MISC_CTL_3 */ #define PD68_MC3_HW_SUSP … #define PD68_MC3_MM_EXPAND … #define PD68_MC3_MM_ARM … /* Bridge Control Register */ #define PD6832_BCR_MGMT_IRQ_ENA … /* Socket Number Register */ #define PD6832_SOCKET_NUMBER … #endif /* _LINUX_CIRRUS_H */
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