/* SPDX-License-Identifier: GPL-2.0 */ /* * core.h - DesignWare USB3 DRD Core Header * * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com * * Authors: Felipe Balbi <[email protected]>, * Sebastian Andrzej Siewior <[email protected]> */ #ifndef __DRIVERS_USB_DWC3_CORE_H #define __DRIVERS_USB_DWC3_CORE_H #include <linux/device.h> #include <linux/spinlock.h> #include <linux/mutex.h> #include <linux/ioport.h> #include <linux/list.h> #include <linux/bitops.h> #include <linux/dma-mapping.h> #include <linux/mm.h> #include <linux/debugfs.h> #include <linux/wait.h> #include <linux/workqueue.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> #include <linux/usb/otg.h> #include <linux/usb/role.h> #include <linux/ulpi/interface.h> #include <linux/phy/phy.h> #include <linux/power_supply.h> /* * DWC3 Multiport controllers support up to 15 High-Speed PHYs * and 4 SuperSpeed PHYs. */ #define DWC3_USB2_MAX_PORTS … #define DWC3_USB3_MAX_PORTS … #define DWC3_MSG_MAX … /* Global constants */ #define DWC3_PULL_UP_TIMEOUT … #define DWC3_BOUNCE_SIZE … #define DWC3_EP0_SETUP_SIZE … #define DWC3_ENDPOINTS_NUM … #define DWC3_XHCI_RESOURCES_NUM … #define DWC3_ISOC_MAX_RETRIES … #define DWC3_SCRATCHBUF_SIZE … #define DWC3_EVENT_BUFFERS_SIZE … #define DWC3_EVENT_TYPE_MASK … #define DWC3_EVENT_TYPE_DEV … #define DWC3_EVENT_TYPE_CARKIT … #define DWC3_EVENT_TYPE_I2C … #define DWC3_DEVICE_EVENT_DISCONNECT … #define DWC3_DEVICE_EVENT_RESET … #define DWC3_DEVICE_EVENT_CONNECT_DONE … #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE … #define DWC3_DEVICE_EVENT_WAKEUP … #define DWC3_DEVICE_EVENT_HIBER_REQ … #define DWC3_DEVICE_EVENT_SUSPEND … #define DWC3_DEVICE_EVENT_SOF … #define DWC3_DEVICE_EVENT_ERRATIC_ERROR … #define DWC3_DEVICE_EVENT_CMD_CMPL … #define DWC3_DEVICE_EVENT_OVERFLOW … /* Controller's role while using the OTG block */ #define DWC3_OTG_ROLE_IDLE … #define DWC3_OTG_ROLE_HOST … #define DWC3_OTG_ROLE_DEVICE … #define DWC3_GEVNTCOUNT_MASK … #define DWC3_GEVNTCOUNT_EHB … #define DWC3_GSNPSID_MASK … #define DWC3_GSNPSREV_MASK … #define DWC3_GSNPS_ID(p) … /* DWC3 registers memory space boundries */ #define DWC3_XHCI_REGS_START … #define DWC3_XHCI_REGS_END … #define DWC3_GLOBALS_REGS_START … #define DWC3_GLOBALS_REGS_END … #define DWC3_DEVICE_REGS_START … #define DWC3_DEVICE_REGS_END … #define DWC3_OTG_REGS_START … #define DWC3_OTG_REGS_END … #define DWC3_RTK_RTD_GLOBALS_REGS_START … /* Global Registers */ #define DWC3_GSBUSCFG0 … #define DWC3_GSBUSCFG1 … #define DWC3_GTXTHRCFG … #define DWC3_GRXTHRCFG … #define DWC3_GCTL … #define DWC3_GEVTEN … #define DWC3_GSTS … #define DWC3_GUCTL1 … #define DWC3_GSNPSID … #define DWC3_GGPIO … #define DWC3_GUID … #define DWC3_GUCTL … #define DWC3_GBUSERRADDR0 … #define DWC3_GBUSERRADDR1 … #define DWC3_GPRTBIMAP0 … #define DWC3_GPRTBIMAP1 … #define DWC3_GHWPARAMS0 … #define DWC3_GHWPARAMS1 … #define DWC3_GHWPARAMS2 … #define DWC3_GHWPARAMS3 … #define DWC3_GHWPARAMS4 … #define DWC3_GHWPARAMS5 … #define DWC3_GHWPARAMS6 … #define DWC3_GHWPARAMS7 … #define DWC3_GDBGFIFOSPACE … #define DWC3_GDBGLTSSM … #define DWC3_GDBGBMU … #define DWC3_GDBGLSPMUX … #define DWC3_GDBGLSP … #define DWC3_GDBGEPINFO0 … #define DWC3_GDBGEPINFO1 … #define DWC3_GPRTBIMAP_HS0 … #define DWC3_GPRTBIMAP_HS1 … #define DWC3_GPRTBIMAP_FS0 … #define DWC3_GPRTBIMAP_FS1 … #define DWC3_GUCTL2 … #define DWC3_VER_NUMBER … #define DWC3_VER_TYPE … #define DWC3_GUSB2PHYCFG(n) … #define DWC3_GUSB2I2CCTL(n) … #define DWC3_GUSB2PHYACC(n) … #define DWC3_GUSB3PIPECTL(n) … #define DWC3_GTXFIFOSIZ(n) … #define DWC3_GRXFIFOSIZ(n) … #define DWC3_GEVNTADRLO(n) … #define DWC3_GEVNTADRHI(n) … #define DWC3_GEVNTSIZ(n) … #define DWC3_GEVNTCOUNT(n) … #define DWC3_GHWPARAMS8 … #define DWC3_GUCTL3 … #define DWC3_GFLADJ … #define DWC3_GHWPARAMS9 … /* Device Registers */ #define DWC3_DCFG … #define DWC3_DCTL … #define DWC3_DEVTEN … #define DWC3_DSTS … #define DWC3_DGCMDPAR … #define DWC3_DGCMD … #define DWC3_DALEPENA … #define DWC3_DCFG1 … #define DWC3_DEP_BASE(n) … #define DWC3_DEPCMDPAR2 … #define DWC3_DEPCMDPAR1 … #define DWC3_DEPCMDPAR0 … #define DWC3_DEPCMD … #define DWC3_DEV_IMOD(n) … /* OTG Registers */ #define DWC3_OCFG … #define DWC3_OCTL … #define DWC3_OEVT … #define DWC3_OEVTEN … #define DWC3_OSTS … #define DWC3_LLUCTL … /* Bit fields */ /* Global SoC Bus Configuration INCRx Register 0 */ #define DWC3_GSBUSCFG0_INCR256BRSTENA … #define DWC3_GSBUSCFG0_INCR128BRSTENA … #define DWC3_GSBUSCFG0_INCR64BRSTENA … #define DWC3_GSBUSCFG0_INCR32BRSTENA … #define DWC3_GSBUSCFG0_INCR16BRSTENA … #define DWC3_GSBUSCFG0_INCR8BRSTENA … #define DWC3_GSBUSCFG0_INCR4BRSTENA … #define DWC3_GSBUSCFG0_INCRBRSTENA … #define DWC3_GSBUSCFG0_INCRBRST_MASK … /* Global SoC Bus Configuration Register: AHB-prot/AXI-cache/OCP-ReqInfo */ #define DWC3_GSBUSCFG0_REQINFO(n) … #define DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED … /* Global Debug LSP MUX Select */ #define DWC3_GDBGLSPMUX_ENDBC … #define DWC3_GDBGLSPMUX_HOSTSELECT(n) … #define DWC3_GDBGLSPMUX_DEVSELECT(n) … #define DWC3_GDBGLSPMUX_EPSELECT(n) … /* Global Debug Queue/FIFO Space Available Register */ #define DWC3_GDBGFIFOSPACE_NUM(n) … #define DWC3_GDBGFIFOSPACE_TYPE(n) … #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) … #define DWC3_TXFIFO … #define DWC3_RXFIFO … #define DWC3_TXREQQ … #define DWC3_RXREQQ … #define DWC3_RXINFOQ … #define DWC3_PSTATQ … #define DWC3_DESCFETCHQ … #define DWC3_EVENTQ … #define DWC3_AUXEVENTQ … /* Global RX Threshold Configuration Register */ #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) … #define DWC3_GRXTHRCFG_RXPKTCNT(n) … #define DWC3_GRXTHRCFG_PKTCNTSEL … /* Global TX Threshold Configuration Register */ #define DWC3_GTXTHRCFG_MAXTXBURSTSIZE(n) … #define DWC3_GTXTHRCFG_TXPKTCNT(n) … #define DWC3_GTXTHRCFG_PKTCNTSEL … /* Global RX Threshold Configuration Register for DWC_usb31 only */ #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) … #define DWC31_GRXTHRCFG_RXPKTCNT(n) … #define DWC31_GRXTHRCFG_PKTCNTSEL … #define DWC31_RXTHRNUMPKTSEL_HS_PRD … #define DWC31_RXTHRNUMPKT_HS_PRD(n) … #define DWC31_RXTHRNUMPKTSEL_PRD … #define DWC31_RXTHRNUMPKT_PRD(n) … #define DWC31_MAXRXBURSTSIZE_PRD(n) … /* Global TX Threshold Configuration Register for DWC_usb31 only */ #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) … #define DWC31_GTXTHRCFG_TXPKTCNT(n) … #define DWC31_GTXTHRCFG_PKTCNTSEL … #define DWC31_TXTHRNUMPKTSEL_HS_PRD … #define DWC31_TXTHRNUMPKT_HS_PRD(n) … #define DWC31_TXTHRNUMPKTSEL_PRD … #define DWC31_TXTHRNUMPKT_PRD(n) … #define DWC31_MAXTXBURSTSIZE_PRD(n) … /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) … #define DWC3_GCTL_PWRDNSCALE_MASK … #define DWC3_GCTL_U2RSTECN … #define DWC3_GCTL_RAMCLKSEL(x) … #define DWC3_GCTL_CLK_BUS … #define DWC3_GCTL_CLK_PIPE … #define DWC3_GCTL_CLK_PIPEHALF … #define DWC3_GCTL_CLK_MASK … #define DWC3_GCTL_PRTCAP(n) … #define DWC3_GCTL_PRTCAPDIR(n) … #define DWC3_GCTL_PRTCAP_HOST … #define DWC3_GCTL_PRTCAP_DEVICE … #define DWC3_GCTL_PRTCAP_OTG … #define DWC3_GCTL_CORESOFTRESET … #define DWC3_GCTL_SOFITPSYNC … #define DWC3_GCTL_SCALEDOWN(n) … #define DWC3_GCTL_SCALEDOWN_MASK … #define DWC3_GCTL_DISSCRAMBLE … #define DWC3_GCTL_U2EXIT_LFPS … #define DWC3_GCTL_GBLHIBERNATIONEN … #define DWC3_GCTL_DSBLCLKGTNG … /* Global User Control 1 Register */ #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT … #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS … #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK … #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW … #define DWC3_GUCTL1_PARKMODE_DISABLE_SS … #define DWC3_GUCTL1_PARKMODE_DISABLE_HS … #define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST … /* Global Status Register */ #define DWC3_GSTS_OTG_IP … #define DWC3_GSTS_BC_IP … #define DWC3_GSTS_ADP_IP … #define DWC3_GSTS_HOST_IP … #define DWC3_GSTS_DEVICE_IP … #define DWC3_GSTS_CSR_TIMEOUT … #define DWC3_GSTS_BUS_ERR_ADDR_VLD … #define DWC3_GSTS_CURMOD(n) … #define DWC3_GSTS_CURMOD_DEVICE … #define DWC3_GSTS_CURMOD_HOST … /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST … #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS … #define DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV … #define DWC3_GUSB2PHYCFG_SUSPHY … #define DWC3_GUSB2PHYCFG_ULPI_UTMI … #define DWC3_GUSB2PHYCFG_ENBLSLPM … #define DWC3_GUSB2PHYCFG_PHYIF(n) … #define DWC3_GUSB2PHYCFG_PHYIF_MASK … #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) … #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK … #define USBTRDTIM_UTMI_8_BIT … #define USBTRDTIM_UTMI_16_BIT … #define UTMI_PHYIF_16_BIT … #define UTMI_PHYIF_8_BIT … /* Global USB2 PHY Vendor Control Register */ #define DWC3_GUSB2PHYACC_NEWREGREQ … #define DWC3_GUSB2PHYACC_DONE … #define DWC3_GUSB2PHYACC_BUSY … #define DWC3_GUSB2PHYACC_WRITE … #define DWC3_GUSB2PHYACC_ADDR(n) … #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) … #define DWC3_GUSB2PHYACC_DATA(n) … /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST … #define DWC3_GUSB3PIPECTL_U2SSINP3OK … #define DWC3_GUSB3PIPECTL_DISRXDETINP3 … #define DWC3_GUSB3PIPECTL_UX_EXIT_PX … #define DWC3_GUSB3PIPECTL_REQP1P2P3 … #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) … #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK … #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN … #define DWC3_GUSB3PIPECTL_DEPOCHANGE … #define DWC3_GUSB3PIPECTL_SUSPHY … #define DWC3_GUSB3PIPECTL_LFPSFILT … #define DWC3_GUSB3PIPECTL_RX_DETOPOLL … #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK … #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) … /* Global TX Fifo Size Register */ #define DWC31_GTXFIFOSIZ_TXFRAMNUM … #define DWC31_GTXFIFOSIZ_TXFDEP(n) … #define DWC3_GTXFIFOSIZ_TXFDEP(n) … #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) … /* Global RX Fifo Size Register */ #define DWC31_GRXFIFOSIZ_RXFDEP(n) … #define DWC3_GRXFIFOSIZ_RXFDEP(n) … /* Global Event Size Registers */ #define DWC3_GEVNTSIZ_INTMASK … #define DWC3_GEVNTSIZ_SIZE(n) … /* Global HWPARAMS0 Register */ #define DWC3_GHWPARAMS0_MODE(n) … #define DWC3_GHWPARAMS0_MODE_GADGET … #define DWC3_GHWPARAMS0_MODE_HOST … #define DWC3_GHWPARAMS0_MODE_DRD … #define DWC3_GHWPARAMS0_MBUS_TYPE(n) … #define DWC3_GHWPARAMS0_SBUS_TYPE(n) … #define DWC3_GHWPARAMS0_MDWIDTH(n) … #define DWC3_GHWPARAMS0_SDWIDTH(n) … #define DWC3_GHWPARAMS0_AWIDTH(n) … /* Global HWPARAMS1 Register */ #define DWC3_GHWPARAMS1_EN_PWROPT(n) … #define DWC3_GHWPARAMS1_EN_PWROPT_NO … #define DWC3_GHWPARAMS1_EN_PWROPT_CLK … #define DWC3_GHWPARAMS1_EN_PWROPT_HIB … #define DWC3_GHWPARAMS1_PWROPT(n) … #define DWC3_GHWPARAMS1_PWROPT_MASK … #define DWC3_GHWPARAMS1_ENDBC … /* Global HWPARAMS3 Register */ #define DWC3_GHWPARAMS3_SSPHY_IFC(n) … #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS … #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 … #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 … #define DWC3_GHWPARAMS3_HSPHY_IFC(n) … #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS … #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI … #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI … #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI … #define DWC3_GHWPARAMS3_FSPHY_IFC(n) … #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS … #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA … /* Global HWPARAMS4 Register */ #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) … #define DWC3_MAX_HIBER_SCRATCHBUFS … /* Global HWPARAMS6 Register */ #define DWC3_GHWPARAMS6_BCSUPPORT … #define DWC3_GHWPARAMS6_OTG3SUPPORT … #define DWC3_GHWPARAMS6_ADPSUPPORT … #define DWC3_GHWPARAMS6_HNPSUPPORT … #define DWC3_GHWPARAMS6_SRPSUPPORT … #define DWC3_GHWPARAMS6_EN_FPGA … /* DWC_usb32 only */ #define DWC3_GHWPARAMS6_MDWIDTH(n) … /* Global HWPARAMS7 Register */ #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) … #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) … /* Global HWPARAMS9 Register */ #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS … #define DWC3_GHWPARAMS9_DEV_MST … /* Global Frame Length Adjustment Register */ #define DWC3_GFLADJ_30MHZ_SDBND_SEL … #define DWC3_GFLADJ_30MHZ_MASK … #define DWC3_GFLADJ_REFCLK_FLADJ_MASK … #define DWC3_GFLADJ_REFCLK_LPM_SEL … #define DWC3_GFLADJ_240MHZDECR … #define DWC3_GFLADJ_240MHZDECR_PLS1 … /* Global User Control Register*/ #define DWC3_GUCTL_REFCLKPER_MASK … #define DWC3_GUCTL_REFCLKPER_SEL … /* Global User Control Register 2 */ #define DWC3_GUCTL2_RST_ACTBITLATER … /* Global User Control Register 3 */ #define DWC3_GUCTL3_SPLITDISABLE … /* Device Configuration Register */ #define DWC3_DCFG_NUMLANES(n) … #define DWC3_DCFG_DEVADDR(addr) … #define DWC3_DCFG_DEVADDR_MASK … #define DWC3_DCFG_SPEED_MASK … #define DWC3_DCFG_SUPERSPEED_PLUS … #define DWC3_DCFG_SUPERSPEED … #define DWC3_DCFG_HIGHSPEED … #define DWC3_DCFG_FULLSPEED … #define DWC3_DCFG_NUMP_SHIFT … #define DWC3_DCFG_NUMP(n) … #define DWC3_DCFG_NUMP_MASK … #define DWC3_DCFG_LPM_CAP … #define DWC3_DCFG_IGNSTRMPP … /* Device Control Register */ #define DWC3_DCTL_RUN_STOP … #define DWC3_DCTL_CSFTRST … #define DWC3_DCTL_LSFTRST … #define DWC3_DCTL_HIRD_THRES_MASK … #define DWC3_DCTL_HIRD_THRES(n) … #define DWC3_DCTL_APPL1RES … /* These apply for core versions 1.87a and earlier */ #define DWC3_DCTL_TRGTULST_MASK … #define DWC3_DCTL_TRGTULST(n) … #define DWC3_DCTL_TRGTULST_U2 … #define DWC3_DCTL_TRGTULST_U3 … #define DWC3_DCTL_TRGTULST_SS_DIS … #define DWC3_DCTL_TRGTULST_RX_DET … #define DWC3_DCTL_TRGTULST_SS_INACT … /* These apply for core versions 1.94a and later */ #define DWC3_DCTL_NYET_THRES(n) … #define DWC3_DCTL_KEEP_CONNECT … #define DWC3_DCTL_L1_HIBER_EN … #define DWC3_DCTL_CRS … #define DWC3_DCTL_CSS … #define DWC3_DCTL_INITU2ENA … #define DWC3_DCTL_ACCEPTU2ENA … #define DWC3_DCTL_INITU1ENA … #define DWC3_DCTL_ACCEPTU1ENA … #define DWC3_DCTL_TSTCTRL_MASK … #define DWC3_DCTL_ULSTCHNGREQ_MASK … #define DWC3_DCTL_ULSTCHNGREQ(n) … #define DWC3_DCTL_ULSTCHNG_NO_ACTION … #define DWC3_DCTL_ULSTCHNG_SS_DISABLED … #define DWC3_DCTL_ULSTCHNG_RX_DETECT … #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE … #define DWC3_DCTL_ULSTCHNG_RECOVERY … #define DWC3_DCTL_ULSTCHNG_COMPLIANCE … #define DWC3_DCTL_ULSTCHNG_LOOPBACK … /* Device Event Enable Register */ #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN … #define DWC3_DEVTEN_EVNTOVERFLOWEN … #define DWC3_DEVTEN_CMDCMPLTEN … #define DWC3_DEVTEN_ERRTICERREN … #define DWC3_DEVTEN_SOFEN … #define DWC3_DEVTEN_U3L2L1SUSPEN … #define DWC3_DEVTEN_HIBERNATIONREQEVTEN … #define DWC3_DEVTEN_WKUPEVTEN … #define DWC3_DEVTEN_ULSTCNGEN … #define DWC3_DEVTEN_CONNECTDONEEN … #define DWC3_DEVTEN_USBRSTEN … #define DWC3_DEVTEN_DISCONNEVTEN … #define DWC3_DSTS_CONNLANES(n) … /* Device Status Register */ #define DWC3_DSTS_DCNRD … /* This applies for core versions 1.87a and earlier */ #define DWC3_DSTS_PWRUPREQ … /* These apply for core versions 1.94a and later */ #define DWC3_DSTS_RSS … #define DWC3_DSTS_SSS … #define DWC3_DSTS_COREIDLE … #define DWC3_DSTS_DEVCTRLHLT … #define DWC3_DSTS_USBLNKST_MASK … #define DWC3_DSTS_USBLNKST(n) … #define DWC3_DSTS_RXFIFOEMPTY … #define DWC3_DSTS_SOFFN_MASK … #define DWC3_DSTS_SOFFN(n) … #define DWC3_DSTS_CONNECTSPD … #define DWC3_DSTS_SUPERSPEED_PLUS … #define DWC3_DSTS_SUPERSPEED … #define DWC3_DSTS_HIGHSPEED … #define DWC3_DSTS_FULLSPEED … /* Device Generic Command Register */ #define DWC3_DGCMD_SET_LMP … #define DWC3_DGCMD_SET_PERIODIC_PAR … #define DWC3_DGCMD_XMIT_FUNCTION … /* These apply for core versions 1.94a and later */ #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO … #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI … #define DWC3_DGCMD_SELECTED_FIFO_FLUSH … #define DWC3_DGCMD_ALL_FIFO_FLUSH … #define DWC3_DGCMD_SET_ENDPOINT_NRDY … #define DWC3_DGCMD_SET_ENDPOINT_PRIME … #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK … #define DWC3_DGCMD_DEV_NOTIFICATION … #define DWC3_DGCMD_STATUS(n) … #define DWC3_DGCMD_CMDACT … #define DWC3_DGCMD_CMDIOC … /* Device Generic Command Parameter Register */ #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT … #define DWC3_DGCMDPAR_FIFO_NUM(n) … #define DWC3_DGCMDPAR_RX_FIFO … #define DWC3_DGCMDPAR_TX_FIFO … #define DWC3_DGCMDPAR_LOOPBACK_DIS … #define DWC3_DGCMDPAR_LOOPBACK_ENA … #define DWC3_DGCMDPAR_DN_FUNC_WAKE … #define DWC3_DGCMDPAR_INTF_SEL(n) … /* Device Endpoint Command Register */ #define DWC3_DEPCMD_PARAM_SHIFT … #define DWC3_DEPCMD_PARAM(x) … #define DWC3_DEPCMD_GET_RSC_IDX(x) … #define DWC3_DEPCMD_STATUS(x) … #define DWC3_DEPCMD_HIPRI_FORCERM … #define DWC3_DEPCMD_CLEARPENDIN … #define DWC3_DEPCMD_CMDACT … #define DWC3_DEPCMD_CMDIOC … #define DWC3_DEPCMD_DEPSTARTCFG … #define DWC3_DEPCMD_ENDTRANSFER … #define DWC3_DEPCMD_UPDATETRANSFER … #define DWC3_DEPCMD_STARTTRANSFER … #define DWC3_DEPCMD_CLEARSTALL … #define DWC3_DEPCMD_SETSTALL … /* This applies for core versions 1.90a and earlier */ #define DWC3_DEPCMD_GETSEQNUMBER … /* This applies for core versions 1.94a and later */ #define DWC3_DEPCMD_GETEPSTATE … #define DWC3_DEPCMD_SETTRANSFRESOURCE … #define DWC3_DEPCMD_SETEPCONFIG … #define DWC3_DEPCMD_CMD(x) … /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ #define DWC3_DALEPENA_EP(n) … /* DWC_usb32 DCFG1 config */ #define DWC3_DCFG1_DIS_MST_ENH … #define DWC3_DEPCMD_TYPE_CONTROL … #define DWC3_DEPCMD_TYPE_ISOC … #define DWC3_DEPCMD_TYPE_BULK … #define DWC3_DEPCMD_TYPE_INTR … #define DWC3_DEV_IMOD_COUNT_SHIFT … #define DWC3_DEV_IMOD_COUNT_MASK … #define DWC3_DEV_IMOD_INTERVAL_SHIFT … #define DWC3_DEV_IMOD_INTERVAL_MASK … /* OTG Configuration Register */ #define DWC3_OCFG_DISPWRCUTTOFF … #define DWC3_OCFG_HIBDISMASK … #define DWC3_OCFG_SFTRSTMASK … #define DWC3_OCFG_OTGVERSION … #define DWC3_OCFG_HNPCAP … #define DWC3_OCFG_SRPCAP … /* OTG CTL Register */ #define DWC3_OCTL_OTG3GOERR … #define DWC3_OCTL_PERIMODE … #define DWC3_OCTL_PRTPWRCTL … #define DWC3_OCTL_HNPREQ … #define DWC3_OCTL_SESREQ … #define DWC3_OCTL_TERMSELIDPULSE … #define DWC3_OCTL_DEVSETHNPEN … #define DWC3_OCTL_HSTSETHNPEN … /* OTG Event Register */ #define DWC3_OEVT_DEVICEMODE … #define DWC3_OEVT_XHCIRUNSTPSET … #define DWC3_OEVT_DEVRUNSTPSET … #define DWC3_OEVT_HIBENTRY … #define DWC3_OEVT_CONIDSTSCHNG … #define DWC3_OEVT_HRRCONFNOTIF … #define DWC3_OEVT_HRRINITNOTIF … #define DWC3_OEVT_ADEVIDLE … #define DWC3_OEVT_ADEVBHOSTEND … #define DWC3_OEVT_ADEVHOST … #define DWC3_OEVT_ADEVHNPCHNG … #define DWC3_OEVT_ADEVSRPDET … #define DWC3_OEVT_ADEVSESSENDDET … #define DWC3_OEVT_BDEVBHOSTEND … #define DWC3_OEVT_BDEVHNPCHNG … #define DWC3_OEVT_BDEVSESSVLDDET … #define DWC3_OEVT_BDEVVBUSCHNG … #define DWC3_OEVT_BSESSVLD … #define DWC3_OEVT_HSTNEGSTS … #define DWC3_OEVT_SESREQSTS … #define DWC3_OEVT_ERROR … /* OTG Event Enable Register */ #define DWC3_OEVTEN_XHCIRUNSTPSETEN … #define DWC3_OEVTEN_DEVRUNSTPSETEN … #define DWC3_OEVTEN_HIBENTRYEN … #define DWC3_OEVTEN_CONIDSTSCHNGEN … #define DWC3_OEVTEN_HRRCONFNOTIFEN … #define DWC3_OEVTEN_HRRINITNOTIFEN … #define DWC3_OEVTEN_ADEVIDLEEN … #define DWC3_OEVTEN_ADEVBHOSTENDEN … #define DWC3_OEVTEN_ADEVHOSTEN … #define DWC3_OEVTEN_ADEVHNPCHNGEN … #define DWC3_OEVTEN_ADEVSRPDETEN … #define DWC3_OEVTEN_ADEVSESSENDDETEN … #define DWC3_OEVTEN_BDEVBHOSTENDEN … #define DWC3_OEVTEN_BDEVHNPCHNGEN … #define DWC3_OEVTEN_BDEVSESSVLDDETEN … #define DWC3_OEVTEN_BDEVVBUSCHNGEN … /* OTG Status Register */ #define DWC3_OSTS_DEVRUNSTP … #define DWC3_OSTS_XHCIRUNSTP … #define DWC3_OSTS_PERIPHERALSTATE … #define DWC3_OSTS_XHCIPRTPOWER … #define DWC3_OSTS_BSESVLD … #define DWC3_OSTS_VBUSVLD … #define DWC3_OSTS_CONIDSTS … /* Force Gen1 speed on Gen2 link */ #define DWC3_LLUCTL_FORCE_GEN1 … /* Structures */ struct dwc3_trb; /** * struct dwc3_event_buffer - Software event buffer representation * @buf: _THE_ buffer * @cache: The buffer cache used in the threaded interrupt * @length: size of this buffer * @lpos: event offset * @count: cache of last read event count register * @flags: flags related to this event buffer * @dma: dma_addr_t * @dwc: pointer to DWC controller */ struct dwc3_event_buffer { … }; #define DWC3_EP_FLAG_STALLED … #define DWC3_EP_FLAG_WEDGED … #define DWC3_EP_DIRECTION_TX … #define DWC3_EP_DIRECTION_RX … #define DWC3_TRB_NUM … /** * struct dwc3_ep - device side endpoint representation * @endpoint: usb endpoint * @cancelled_list: list of cancelled requests for this endpoint * @pending_list: list of pending requests for this endpoint * @started_list: list of started requests on this endpoint * @regs: pointer to first endpoint register * @trb_pool: array of transaction buffers * @trb_pool_dma: dma address of @trb_pool * @trb_enqueue: enqueue 'pointer' into TRB array * @trb_dequeue: dequeue 'pointer' into TRB array * @dwc: pointer to DWC controller * @saved_state: ep state saved during hibernation * @flags: endpoint flags (wedged, stalled, ...) * @number: endpoint number (1 - 15) * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK * @resource_index: Resource transfer index * @frame_number: set to the frame number we want this transfer to start (ISOC) * @interval: the interval on which the ISOC transfer is started * @name: a human readable name e.g. ep1out-bulk * @direction: true for TX, false for RX * @stream_capable: true when streams are enabled * @combo_num: the test combination BIT[15:14] of the frame number to test * isochronous START TRANSFER command failure workaround * @start_cmd_status: the status of testing START TRANSFER command with * combo_num = 'b00 */ struct dwc3_ep { … }; enum dwc3_phy { … }; enum dwc3_ep0_next { … }; enum dwc3_ep0_state { … }; enum dwc3_link_state { … }; /* TRB Length, PCM and Status */ #define DWC3_TRB_SIZE_MASK … #define DWC3_TRB_SIZE_LENGTH(n) … #define DWC3_TRB_SIZE_PCM1(n) … #define DWC3_TRB_SIZE_TRBSTS(n) … #define DWC3_TRBSTS_OK … #define DWC3_TRBSTS_MISSED_ISOC … #define DWC3_TRBSTS_SETUP_PENDING … #define DWC3_TRB_STS_XFER_IN_PROG … /* TRB Control */ #define DWC3_TRB_CTRL_HWO … #define DWC3_TRB_CTRL_LST … #define DWC3_TRB_CTRL_CHN … #define DWC3_TRB_CTRL_CSP … #define DWC3_TRB_CTRL_TRBCTL(n) … #define DWC3_TRB_CTRL_ISP_IMI … #define DWC3_TRB_CTRL_IOC … #define DWC3_TRB_CTRL_SID_SOFN(n) … #define DWC3_TRB_CTRL_GET_SID_SOFN(n) … #define DWC3_TRBCTL_TYPE(n) … #define DWC3_TRBCTL_NORMAL … #define DWC3_TRBCTL_CONTROL_SETUP … #define DWC3_TRBCTL_CONTROL_STATUS2 … #define DWC3_TRBCTL_CONTROL_STATUS3 … #define DWC3_TRBCTL_CONTROL_DATA … #define DWC3_TRBCTL_ISOCHRONOUS_FIRST … #define DWC3_TRBCTL_ISOCHRONOUS … #define DWC3_TRBCTL_LINK_TRB … /** * struct dwc3_trb - transfer request block (hw format) * @bpl: DW0-3 * @bph: DW4-7 * @size: DW8-B * @ctrl: DWC-F */ struct dwc3_trb { … } __packed; /** * struct dwc3_hwparams - copy of HWPARAMS registers * @hwparams0: GHWPARAMS0 * @hwparams1: GHWPARAMS1 * @hwparams2: GHWPARAMS2 * @hwparams3: GHWPARAMS3 * @hwparams4: GHWPARAMS4 * @hwparams5: GHWPARAMS5 * @hwparams6: GHWPARAMS6 * @hwparams7: GHWPARAMS7 * @hwparams8: GHWPARAMS8 * @hwparams9: GHWPARAMS9 */ struct dwc3_hwparams { … }; /* HWPARAMS0 */ #define DWC3_MODE(n) … /* HWPARAMS1 */ #define DWC3_NUM_INT(n) … /* HWPARAMS3 */ #define DWC3_NUM_IN_EPS_MASK … #define DWC3_NUM_EPS_MASK … #define DWC3_NUM_EPS(p) … #define DWC3_NUM_IN_EPS(p) … /* HWPARAMS7 */ #define DWC3_RAM1_DEPTH(n) … /* HWPARAMS9 */ #define DWC3_MST_CAPABLE(p) … /** * struct dwc3_request - representation of a transfer request * @request: struct usb_request to be transferred * @list: a list_head used for request queueing * @dep: struct dwc3_ep owning this request * @sg: pointer to first incomplete sg * @start_sg: pointer to the sg which should be queued next * @num_pending_sgs: counter to pending sgs * @num_queued_sgs: counter to the number of sgs which already got queued * @remaining: amount of data remaining * @status: internal dwc3 request status tracking * @epnum: endpoint number to which this request refers * @trb: pointer to struct dwc3_trb * @trb_dma: DMA address of @trb * @num_trbs: number of TRBs used by this request * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP * or unaligned OUT) * @direction: IN or OUT direction flag * @mapped: true when request has been dma-mapped */ struct dwc3_request { … }; /* * struct dwc3_scratchpad_array - hibernation scratchpad array * (format defined by hw) */ struct dwc3_scratchpad_array { … }; /** * struct dwc3 - representation of our controller * @drd_work: workqueue used for role swapping * @ep0_trb: trb which is used for the ctrl_req * @bounce: address of bounce buffer * @setup_buf: used while precessing STD USB requests * @ep0_trb_addr: dma address of @ep0_trb * @bounce_addr: dma address of @bounce * @ep0_usb_req: dummy req used while handling STD USB requests * @ep0_in_setup: one control transfer is completed and enter setup phase * @lock: for synchronizing * @mutex: for mode switching * @dev: pointer to our struct device * @sysdev: pointer to the DMA-capable device * @xhci: pointer to our xHCI child * @xhci_resources: struct resources for our @xhci child * @ev_buf: struct dwc3_event_buffer pointer * @eps: endpoint array * @gadget: device side representation of the peripheral controller * @gadget_driver: pointer to the gadget driver * @bus_clk: clock for accessing the registers * @ref_clk: reference clock * @susp_clk: clock used when the SS phy is in low power (S3) state * @utmi_clk: clock used for USB2 PHY communication * @pipe_clk: clock used for USB3 PHY communication * @reset: reset control * @regs: base address for our registers * @regs_size: address space size * @fladj: frame length adjustment * @ref_clk_per: reference clock period configuration * @irq_gadget: peripheral controller's IRQ number * @otg_irq: IRQ number for OTG IRQs * @current_otg_role: current role of operation while using the OTG block * @desired_otg_role: desired role of operation while using the OTG block * @otg_restart_host: flag that OTG controller needs to restart host * @u1u2: only used on revisions <1.83a for workaround * @maximum_speed: maximum speed requested (mainly for testing purposes) * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count * @gadget_max_speed: maximum gadget speed requested * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling * rate and lane count. * @ip: controller's ID * @revision: controller's version of an IP * @version_type: VERSIONTYPE register contents, a sub release of a revision * @dr_mode: requested mode of operation * @current_dr_role: current role of operation when in dual-role mode * @desired_dr_role: desired role of operation when in dual-role mode * @edev: extcon handle * @edev_nb: extcon notifier * @hsphy_mode: UTMI phy mode, one of following: * - USBPHY_INTERFACE_MODE_UTMI * - USBPHY_INTERFACE_MODE_UTMIW * @role_sw: usb_role_switch handle * @role_switch_default_mode: default operation mode of controller while * usb role is USB_ROLE_NONE. * @usb_psy: pointer to power supply interface. * @usb2_phy: pointer to USB2 PHY * @usb3_phy: pointer to USB3 PHY * @usb2_generic_phy: pointer to array of USB2 PHYs * @usb3_generic_phy: pointer to array of USB3 PHYs * @num_usb2_ports: number of USB2 ports * @num_usb3_ports: number of USB3 ports * @phys_ready: flag to indicate that PHYs are ready * @ulpi: pointer to ulpi interface * @ulpi_ready: flag to indicate that ULPI is initialized * @u2sel: parameter from Set SEL request. * @u2pel: parameter from Set SEL request. * @u1sel: parameter from Set SEL request. * @u1pel: parameter from Set SEL request. * @num_eps: number of endpoints * @ep0_next_event: hold the next expected event * @ep0state: state of endpoint zero * @link_state: link state * @speed: device speed (super, high, full, low) * @hwparams: copy of hwparams registers * @regset: debugfs pointer to regdump file * @dbg_lsp_select: current debug lsp mux register selection * @test_mode: true when we're entering a USB test mode * @test_mode_nr: test feature selector * @lpm_nyet_threshold: LPM NYET response threshold * @hird_threshold: HIRD threshold * @rx_thr_num_pkt: USB receive packet count * @rx_max_burst: max USB receive burst size * @tx_thr_num_pkt: USB transmit packet count * @tx_max_burst: max USB transmit burst size * @rx_thr_num_pkt_prd: periodic ESS receive packet count * @rx_max_burst_prd: max periodic ESS receive burst size * @tx_thr_num_pkt_prd: periodic ESS transmit packet count * @tx_max_burst_prd: max periodic ESS transmit burst size * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize * @clear_stall_protocol: endpoint number that requires a delayed status phase * @hsphy_interface: "utmi" or "ulpi" * @connected: true when we're connected to a host, false otherwise * @softconnect: true when gadget connect is called, false when disconnect runs * @delayed_status: true when gadget driver asks for delayed status * @ep0_bounced: true when we used bounce buffer * @ep0_expect_in: true when we expect a DATA IN transfer * @sysdev_is_parent: true when dwc3 device has a parent driver * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that * there's now way for software to detect this in runtime. * @is_utmi_l1_suspend: the core asserts output signal * 0 - utmi_sleep_n * 1 - utmi_l1_suspend_n * @is_fpga: true when we are using the FPGA board * @pending_events: true when we have pending IRQs to be handled * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints * @pullups_connected: true when Run/Stop bit is set * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround * @three_stage_setup: set if we perform a three phase setup * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is * not needed for DWC_usb31 version 1.70a-ea06 and below * @usb3_lpm_capable: set if hadrware supports Link Power Management * @usb2_lpm_disable: set to disable usb2 lpm for host * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget * @disable_scramble_quirk: set if we enable the disable scramble quirk * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk * @lfps_filter_quirk: set if we enable LFPS filter quirk * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, * disabling the suspend signal to the PHY. * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 * @async_callbacks: if set, indicate that async callbacks will be used. * * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists * in GUSB2PHYCFG, specify that USB2 PHY doesn't * provide a free-running PHY clock. * @dis_del_phy_power_chg_quirk: set if we disable delay phy power * change quirk. * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate * check during HS transmit. * @resume_hs_terminations: Set if we enable quirk for fixing improper crc * generation after resume from suspend. * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin * VBUS with an external supply. * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed * instances in park mode. * @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed * instances in park mode. * @gfladj_refclk_lpm_sel: set if we need to enable SOF/ITP counter * running based on ref_clk * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk * @tx_de_emphasis: Tx de-emphasis value * 0 - -6dB de-emphasis * 1 - -3.5dB de-emphasis * 2 - No de-emphasis * 3 - Reserved * @dis_metastability_quirk: set to disable metastability quirk. * @dis_split_quirk: set to disable split boundary. * @sys_wakeup: set if the device may do system wakeup. * @wakeup_configured: set if the device is configured for remote wakeup. * @suspended: set to track suspend event due to U3/L2. * @imod_interval: set the interrupt moderation interval in 250ns * increments or 0 to disable. * @max_cfg_eps: current max number of IN eps used across all USB configs. * @last_fifo_depth: last fifo depth used to determine next fifo ram start * address. * @num_ep_resized: carries the current number endpoints which have had its tx * fifo resized. * @debug_root: root debugfs directory for this device to put its files in. * @gsbuscfg0_reqinfo: store GSBUSCFG0.DATRDREQINFO, DESRDREQINFO, * DATWRREQINFO, and DESWRREQINFO value passed from * glue driver. */ struct dwc3 { … }; #define INCRX_BURST_MODE … #define INCRX_UNDEF_LENGTH_BURST_MODE … #define work_to_dwc(w) … /* -------------------------------------------------------------------------- */ struct dwc3_event_type { … } __packed; #define DWC3_DEPEVT_XFERCOMPLETE … #define DWC3_DEPEVT_XFERINPROGRESS … #define DWC3_DEPEVT_XFERNOTREADY … #define DWC3_DEPEVT_RXTXFIFOEVT … #define DWC3_DEPEVT_STREAMEVT … #define DWC3_DEPEVT_EPCMDCMPLT … /** * struct dwc3_event_depevt - Device Endpoint Events * @one_bit: indicates this is an endpoint event (not used) * @endpoint_number: number of the endpoint * @endpoint_event: The event we have: * 0x00 - Reserved * 0x01 - XferComplete * 0x02 - XferInProgress * 0x03 - XferNotReady * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) * 0x05 - Reserved * 0x06 - StreamEvt * 0x07 - EPCmdCmplt * @reserved11_10: Reserved, don't use. * @status: Indicates the status of the event. Refer to databook for * more information. * @parameters: Parameters of the current event. Refer to databook for * more information. */ struct dwc3_event_depevt { … } __packed; /** * struct dwc3_event_devt - Device Events * @one_bit: indicates this is a non-endpoint event (not used) * @device_event: indicates it's a device event. Should read as 0x00 * @type: indicates the type of device event. * 0 - DisconnEvt * 1 - USBRst * 2 - ConnectDone * 3 - ULStChng * 4 - WkUpEvt * 5 - Reserved * 6 - Suspend (EOPF on revisions 2.10a and prior) * 7 - SOF * 8 - Reserved * 9 - ErrticErr * 10 - CmdCmplt * 11 - EvntOverflow * 12 - VndrDevTstRcved * @reserved15_12: Reserved, not used * @event_info: Information about this event * @reserved31_25: Reserved, not used */ struct dwc3_event_devt { … } __packed; /** * struct dwc3_event_gevt - Other Core Events * @one_bit: indicates this is a non-endpoint event (not used) * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. * @phy_port_number: self-explanatory * @reserved31_12: Reserved, not used. */ struct dwc3_event_gevt { … } __packed; /** * union dwc3_event - representation of Event Buffer contents * @raw: raw 32-bit event * @type: the type of the event * @depevt: Device Endpoint Event * @devt: Device Event * @gevt: Global Event */ dwc3_event; /** * struct dwc3_gadget_ep_cmd_params - representation of endpoint command * parameters * @param2: third parameter * @param1: second parameter * @param0: first parameter */ struct dwc3_gadget_ep_cmd_params { … }; /* * DWC3 Features to be used as Driver Data */ #define DWC3_HAS_PERIPHERAL … #define DWC3_HAS_XHCI … #define DWC3_HAS_OTG … /* prototypes */ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); void dwc3_set_mode(struct dwc3 *dwc, u32 mode); u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); #define DWC3_IP_IS(_ip) … #define DWC3_VER_IS(_ip, _ver) … #define DWC3_VER_IS_PRIOR(_ip, _ver) … #define DWC3_VER_IS_WITHIN(_ip, _from, _to) … #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) … /** * dwc3_mdwidth - get MDWIDTH value in bits * @dwc: pointer to our context structure * * Return MDWIDTH configuration value in bits. */ static inline u32 dwc3_mdwidth(struct dwc3 *dwc) { … } bool dwc3_has_imod(struct dwc3 *dwc); int dwc3_event_buffers_setup(struct dwc3 *dwc); void dwc3_event_buffers_cleanup(struct dwc3 *dwc); int dwc3_core_soft_reset(struct dwc3 *dwc); void dwc3_enable_susphy(struct dwc3 *dwc, bool enable); #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) int dwc3_host_init(struct dwc3 *dwc); void dwc3_host_exit(struct dwc3 *dwc); #else static inline int dwc3_host_init(struct dwc3 *dwc) { return 0; } static inline void dwc3_host_exit(struct dwc3 *dwc) { } #endif #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) int dwc3_gadget_init(struct dwc3 *dwc); void dwc3_gadget_exit(struct dwc3 *dwc); int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); int dwc3_gadget_get_link_state(struct dwc3 *dwc); int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, struct dwc3_gadget_ep_cmd_params *params); int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, u32 param); void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc); void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status); #else static inline int dwc3_gadget_init(struct dwc3 *dwc) { return 0; } static inline void dwc3_gadget_exit(struct dwc3 *dwc) { } static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) { return 0; } static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) { return 0; } static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) { return 0; } static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, struct dwc3_gadget_ep_cmd_params *params) { return 0; } static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) { return 0; } static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) { } #endif #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) int dwc3_drd_init(struct dwc3 *dwc); void dwc3_drd_exit(struct dwc3 *dwc); void dwc3_otg_init(struct dwc3 *dwc); void dwc3_otg_exit(struct dwc3 *dwc); void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); void dwc3_otg_host_init(struct dwc3 *dwc); #else static inline int dwc3_drd_init(struct dwc3 *dwc) { return 0; } static inline void dwc3_drd_exit(struct dwc3 *dwc) { } static inline void dwc3_otg_init(struct dwc3 *dwc) { } static inline void dwc3_otg_exit(struct dwc3 *dwc) { } static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) { } static inline void dwc3_otg_host_init(struct dwc3 *dwc) { } #endif /* power management interface */ #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) int dwc3_gadget_suspend(struct dwc3 *dwc); int dwc3_gadget_resume(struct dwc3 *dwc); void dwc3_gadget_process_pending_events(struct dwc3 *dwc); #else static inline int dwc3_gadget_suspend(struct dwc3 *dwc) { return 0; } static inline int dwc3_gadget_resume(struct dwc3 *dwc) { return 0; } static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) { } #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) int dwc3_ulpi_init(struct dwc3 *dwc); void dwc3_ulpi_exit(struct dwc3 *dwc); #else static inline int dwc3_ulpi_init(struct dwc3 *dwc) { return 0; } static inline void dwc3_ulpi_exit(struct dwc3 *dwc) { } #endif #endif /* __DRIVERS_USB_DWC3_CORE_H */
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