// SPDX-License-Identifier: GPL-2.0 /* * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com */ #include <linux/init.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/pm_runtime.h> #include <linux/clk.h> #include <linux/regmap.h> #include <linux/pinctrl/consumer.h> #include "core.h" /* USB WRAPPER register offsets */ #define USBSS_PID … #define USBSS_OVERCURRENT_CTRL … #define USBSS_PHY_CONFIG … #define USBSS_PHY_TEST … #define USBSS_CORE_STAT … #define USBSS_HOST_VBUS_CTRL … #define USBSS_MODE_CONTROL … #define USBSS_WAKEUP_CONFIG … #define USBSS_WAKEUP_STAT … #define USBSS_OVERRIDE_CONFIG … #define USBSS_IRQ_MISC_STATUS_RAW … #define USBSS_IRQ_MISC_STATUS … #define USBSS_IRQ_MISC_ENABLE_SET … #define USBSS_IRQ_MISC_ENABLE_CLR … #define USBSS_IRQ_MISC_EOI … #define USBSS_INTR_TEST … #define USBSS_VBUS_FILTER … #define USBSS_VBUS_STAT … #define USBSS_DEBUG_CFG … #define USBSS_DEBUG_DATA … #define USBSS_HOST_HUB_CTRL … /* PHY CONFIG register bits */ #define USBSS_PHY_VBUS_SEL_MASK … #define USBSS_PHY_VBUS_SEL_SHIFT … #define USBSS_PHY_LANE_REVERSE … /* CORE STAT register bits */ #define USBSS_CORE_OPERATIONAL_MODE_MASK … #define USBSS_CORE_OPERATIONAL_MODE_SHIFT … /* MODE CONTROL register bits */ #define USBSS_MODE_VALID … /* WAKEUP CONFIG register bits */ #define USBSS_WAKEUP_CFG_OVERCURRENT_EN … #define USBSS_WAKEUP_CFG_LINESTATE_EN … #define USBSS_WAKEUP_CFG_SESSVALID_EN … #define USBSS_WAKEUP_CFG_VBUSVALID_EN … #define USBSS_WAKEUP_CFG_ALL … #define USBSS_WAKEUP_CFG_NONE … /* WAKEUP STAT register bits */ #define USBSS_WAKEUP_STAT_OVERCURRENT … #define USBSS_WAKEUP_STAT_LINESTATE … #define USBSS_WAKEUP_STAT_SESSVALID … #define USBSS_WAKEUP_STAT_VBUSVALID … #define USBSS_WAKEUP_STAT_CLR … /* IRQ_MISC_STATUS_RAW register bits */ #define USBSS_IRQ_MISC_RAW_VBUSVALID … #define USBSS_IRQ_MISC_RAW_SESSVALID … /* IRQ_MISC_STATUS register bits */ #define USBSS_IRQ_MISC_VBUSVALID … #define USBSS_IRQ_MISC_SESSVALID … /* IRQ_MISC_ENABLE_SET register bits */ #define USBSS_IRQ_MISC_ENABLE_SET_VBUSVALID … #define USBSS_IRQ_MISC_ENABLE_SET_SESSVALID … /* IRQ_MISC_ENABLE_CLR register bits */ #define USBSS_IRQ_MISC_ENABLE_CLR_VBUSVALID … #define USBSS_IRQ_MISC_ENABLE_CLR_SESSVALID … /* IRQ_MISC_EOI register bits */ #define USBSS_IRQ_MISC_EOI_VECTOR … /* VBUS_STAT register bits */ #define USBSS_VBUS_STAT_SESSVALID … #define USBSS_VBUS_STAT_VBUSVALID … /* USB_PHY_CTRL register bits in CTRL_MMR */ #define PHY_CORE_VOLTAGE_MASK … #define PHY_PLL_REFCLK_MASK … /* USB PHY2 register offsets */ #define USB_PHY_PLL_REG12 … #define USB_PHY_PLL_LDO_REF_EN … #define USB_PHY_PLL_LDO_REF_EN_EN … #define DWC3_AM62_AUTOSUSPEND_DELAY … struct dwc3_am62 { … }; static const int dwc3_ti_rate_table[] = …; static inline u32 dwc3_ti_readl(struct dwc3_am62 *am62, u32 offset) { … } static inline void dwc3_ti_writel(struct dwc3_am62 *am62, u32 offset, u32 value) { … } static int phy_syscon_pll_refclk(struct dwc3_am62 *am62) { … } static int dwc3_ti_probe(struct platform_device *pdev) { … } static void dwc3_ti_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM static int dwc3_ti_suspend_common(struct device *dev) { … } static int dwc3_ti_resume_common(struct device *dev) { … } static UNIVERSAL_DEV_PM_OPS(dwc3_ti_pm_ops, dwc3_ti_suspend_common, dwc3_ti_resume_common, NULL); #define DEV_PM_OPS … #else #define DEV_PM_OPS … #endif /* CONFIG_PM */ static const struct of_device_id dwc3_ti_of_match[] = …; MODULE_DEVICE_TABLE(of, dwc3_ti_of_match); static struct platform_driver dwc3_ti_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_DESCRIPTION(…) …;
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