// SPDX-License-Identifier: GPL-2.0 /* * dwc3-omap.c - OMAP Specific Glue layer * * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com * * Authors: Felipe Balbi <[email protected]>, * Sebastian Andrzej Siewior <[email protected]> */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/slab.h> #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/dma-mapping.h> #include <linux/ioport.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/extcon.h> #include <linux/regulator/consumer.h> #include <linux/usb/otg.h> /* * All these registers belong to OMAP's Wrapper around the * DesignWare USB3 Core. */ #define USBOTGSS_REVISION … #define USBOTGSS_SYSCONFIG … #define USBOTGSS_IRQ_EOI … #define USBOTGSS_EOI_OFFSET … #define USBOTGSS_IRQSTATUS_RAW_0 … #define USBOTGSS_IRQSTATUS_0 … #define USBOTGSS_IRQENABLE_SET_0 … #define USBOTGSS_IRQENABLE_CLR_0 … #define USBOTGSS_IRQ0_OFFSET … #define USBOTGSS_IRQSTATUS_RAW_1 … #define USBOTGSS_IRQSTATUS_1 … #define USBOTGSS_IRQENABLE_SET_1 … #define USBOTGSS_IRQENABLE_CLR_1 … #define USBOTGSS_IRQSTATUS_RAW_2 … #define USBOTGSS_IRQSTATUS_2 … #define USBOTGSS_IRQENABLE_SET_2 … #define USBOTGSS_IRQENABLE_CLR_2 … #define USBOTGSS_IRQSTATUS_RAW_3 … #define USBOTGSS_IRQSTATUS_3 … #define USBOTGSS_IRQENABLE_SET_3 … #define USBOTGSS_IRQENABLE_CLR_3 … #define USBOTGSS_IRQSTATUS_EOI_MISC … #define USBOTGSS_IRQSTATUS_RAW_MISC … #define USBOTGSS_IRQSTATUS_MISC … #define USBOTGSS_IRQENABLE_SET_MISC … #define USBOTGSS_IRQENABLE_CLR_MISC … #define USBOTGSS_IRQMISC_OFFSET … #define USBOTGSS_UTMI_OTG_STATUS … #define USBOTGSS_UTMI_OTG_CTRL … #define USBOTGSS_UTMI_OTG_OFFSET … #define USBOTGSS_TXFIFO_DEPTH … #define USBOTGSS_RXFIFO_DEPTH … #define USBOTGSS_MMRAM_OFFSET … #define USBOTGSS_FLADJ … #define USBOTGSS_DEBUG_CFG … #define USBOTGSS_DEBUG_DATA … #define USBOTGSS_DEV_EBC_EN … #define USBOTGSS_DEBUG_OFFSET … /* SYSCONFIG REGISTER */ #define USBOTGSS_SYSCONFIG_DMADISABLE … /* IRQ_EOI REGISTER */ #define USBOTGSS_IRQ_EOI_LINE_NUMBER … /* IRQS0 BITS */ #define USBOTGSS_IRQO_COREIRQ_ST … /* IRQMISC BITS */ #define USBOTGSS_IRQMISC_DMADISABLECLR … #define USBOTGSS_IRQMISC_OEVT … #define USBOTGSS_IRQMISC_DRVVBUS_RISE … #define USBOTGSS_IRQMISC_CHRGVBUS_RISE … #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE … #define USBOTGSS_IRQMISC_IDPULLUP_RISE … #define USBOTGSS_IRQMISC_DRVVBUS_FALL … #define USBOTGSS_IRQMISC_CHRGVBUS_FALL … #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL … #define USBOTGSS_IRQMISC_IDPULLUP_FALL … /* UTMI_OTG_STATUS REGISTER */ #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS … #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS … #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS … #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP … /* UTMI_OTG_CTRL REGISTER */ #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE … #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT … #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE … #define USBOTGSS_UTMI_OTG_CTRL_IDDIG … #define USBOTGSS_UTMI_OTG_CTRL_SESSEND … #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID … #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID … enum dwc3_omap_utmi_mode { … }; struct dwc3_omap { … }; enum omap_dwc3_vbus_id_status { … }; static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) { … } static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) { … } static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap) { … } static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value) { … } static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) { … } static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) { … } static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) { … } static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) { … } static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) { … } static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) { … } static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) { … } static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) { … } static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, enum omap_dwc3_vbus_id_status status) { … } static void dwc3_omap_enable_irqs(struct dwc3_omap *omap); static void dwc3_omap_disable_irqs(struct dwc3_omap *omap); static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) { … } static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap) { … } static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) { … } static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) { … } static int dwc3_omap_id_notifier(struct notifier_block *nb, unsigned long event, void *ptr) { … } static int dwc3_omap_vbus_notifier(struct notifier_block *nb, unsigned long event, void *ptr) { … } static void dwc3_omap_map_offset(struct dwc3_omap *omap) { … } static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) { … } static int dwc3_omap_extcon_register(struct dwc3_omap *omap) { … } static int dwc3_omap_probe(struct platform_device *pdev) { … } static void dwc3_omap_remove(struct platform_device *pdev) { … } static const struct of_device_id of_dwc3_match[] = …; MODULE_DEVICE_TABLE(of, of_dwc3_match); #ifdef CONFIG_PM_SLEEP static int dwc3_omap_suspend(struct device *dev) { … } static int dwc3_omap_resume(struct device *dev) { … } static void dwc3_omap_complete(struct device *dev) { … } static const struct dev_pm_ops dwc3_omap_dev_pm_ops = …; #define DEV_PM_OPS … #else #define DEV_PM_OPS … #endif /* CONFIG_PM_SLEEP */ static struct platform_driver dwc3_omap_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_DESCRIPTION(…) …;
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