// SPDX-License-Identifier: GPL-2.0 /* * USB Glue for Amlogic G12A SoCs * * Copyright (c) 2019 BayLibre, SAS * Author: Neil Armstrong <[email protected]> */ /* * The USB is organized with a glue around the DWC3 Controller IP as : * - Control registers for each USB2 Ports * - Control registers for the USB PHY layer * - SuperSpeed PHY can be enabled only if port is used * - Dynamic OTG switching with ID change interrupt */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/reset.h> #include <linux/phy/phy.h> #include <linux/usb/otg.h> #include <linux/usb/role.h> #include <linux/regulator/consumer.h> /* USB2 Ports Control Registers, offsets are per-port */ #define U2P_REG_SIZE … #define U2P_R0 … #define U2P_R0_HOST_DEVICE … #define U2P_R0_POWER_OK … #define U2P_R0_HAST_MODE … #define U2P_R0_POWER_ON_RESET … #define U2P_R0_ID_PULLUP … #define U2P_R0_DRV_VBUS … #define U2P_R1 … #define U2P_R1_PHY_READY … #define U2P_R1_ID_DIG … #define U2P_R1_OTG_SESSION_VALID … #define U2P_R1_VBUS_VALID … /* USB Glue Control Registers */ #define G12A_GLUE_OFFSET … #define USB_R0 … #define USB_R0_P30_LANE0_TX2RX_LOOPBACK … #define USB_R0_P30_LANE0_EXT_PCLK_REQ … #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK … #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK … #define USB_R0_U2D_ACT … #define USB_R1 … #define USB_R1_U3H_BIGENDIAN_GS … #define USB_R1_U3H_PME_ENABLE … #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK … #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK … #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK … #define USB_R1_U3H_HOST_U3_PORT_DISABLE … #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT … #define USB_R1_U3H_HOST_MSI_ENABLE … #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK … #define USB_R1_P30_PCS_TX_SWING_FULL_MASK … #define USB_R2 … #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK … #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK … #define USB_R3 … #define USB_R3_P30_SSC_ENABLE … #define USB_R3_P30_SSC_RANGE_MASK … #define USB_R3_P30_SSC_REF_CLK_SEL_MASK … #define USB_R3_P30_REF_SSP_EN … #define USB_R4 … #define USB_R4_P21_PORT_RESET_0 … #define USB_R4_P21_SLEEP_M0 … #define USB_R4_MEM_PD_MASK … #define USB_R4_P21_ONLY … #define USB_R5 … #define USB_R5_ID_DIG_SYNC … #define USB_R5_ID_DIG_REG … #define USB_R5_ID_DIG_CFG_MASK … #define USB_R5_ID_DIG_EN_0 … #define USB_R5_ID_DIG_EN_1 … #define USB_R5_ID_DIG_CURR … #define USB_R5_ID_DIG_IRQ … #define USB_R5_ID_DIG_TH_MASK … #define USB_R5_ID_DIG_CNT_MASK … #define PHY_COUNT … #define USB2_OTG_PHY … static struct clk_bulk_data meson_gxl_clocks[] = …; static struct clk_bulk_data meson_g12a_clocks[] = …; static struct clk_bulk_data meson_a1_clocks[] = …; static const char * const meson_gxm_phy_names[] = …; static const char * const meson_g12a_phy_names[] = …; /* * Amlogic A1 has a single physical PHY, in slot 1, but still has the * two U2 PHY controls register blocks like G12A. * AXG has the similar scheme, thus needs the same tweak. * Handling the first PHY on slot 1 would need a large amount of code * changes, and the current management is generic enough to handle it * correctly when only the "usb2-phy1" phy is specified on-par with the * DT bindings. */ static const char * const meson_a1_phy_names[] = …; struct dwc3_meson_g12a; struct dwc3_meson_g12a_drvdata { … }; static int dwc3_meson_gxl_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base); static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base); static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode); static int dwc3_meson_gxl_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode); static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode); static int dwc3_meson_gxl_set_phy_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode); static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv); static int dwc3_meson_gxl_usb_init(struct dwc3_meson_g12a *priv); static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv); /* * For GXL and GXM SoCs: * USB Phy muxing between the DWC2 Device controller and the DWC3 Host * controller is buggy when switching from Device to Host when USB port * is unpopulated, it causes the DWC3 to hard crash. * When populated (including OTG switching with ID pin), the switch works * like a charm like on the G12A platforms. * In order to still switch from Host to Device on an USB Type-A port, * an U2_PORT_DISABLE bit has been added to disconnect the DWC3 Host * controller from the port, but when used the DWC3 controller must be * reset to recover usage of the port. */ static const struct dwc3_meson_g12a_drvdata gxl_drvdata = …; static const struct dwc3_meson_g12a_drvdata gxm_drvdata = …; static const struct dwc3_meson_g12a_drvdata axg_drvdata = …; static const struct dwc3_meson_g12a_drvdata g12a_drvdata = …; static const struct dwc3_meson_g12a_drvdata a1_drvdata = …; struct dwc3_meson_g12a { … }; static int dwc3_meson_gxl_set_phy_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode) { … } static int dwc3_meson_gxl_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode) { … } static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode) { … } static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode) { … } static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv, enum phy_mode mode) { … } static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv) { … } static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv, enum phy_mode mode) { … } static int dwc3_meson_g12a_usb_init_glue(struct dwc3_meson_g12a *priv, enum phy_mode mode) { … } static const struct regmap_config phy_meson_g12a_usb_glue_regmap_conf = …; static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv) { … } static enum phy_mode dwc3_meson_g12a_get_id(struct dwc3_meson_g12a *priv) { … } static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv, enum phy_mode mode) { … } static int dwc3_meson_g12a_role_set(struct usb_role_switch *sw, enum usb_role role) { … } static enum usb_role dwc3_meson_g12a_role_get(struct usb_role_switch *sw) { … } static irqreturn_t dwc3_meson_g12a_irq_thread(int irq, void *data) { … } static struct device *dwc3_meson_g12_find_child(struct device *dev, const char *compatible) { … } static int dwc3_meson_g12a_otg_init(struct platform_device *pdev, struct dwc3_meson_g12a *priv) { … } static int dwc3_meson_gxl_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base) { … } static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base) { … } static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) { … } static int dwc3_meson_gxl_usb_init(struct dwc3_meson_g12a *priv) { … } static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv) { … } static int dwc3_meson_g12a_probe(struct platform_device *pdev) { … } static void dwc3_meson_g12a_remove(struct platform_device *pdev) { … } static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev) { … } static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev) { … } static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev) { … } static int __maybe_unused dwc3_meson_g12a_resume(struct device *dev) { … } static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = …; static const struct of_device_id dwc3_meson_g12a_match[] = …; MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match); static struct platform_driver dwc3_meson_g12a_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …;
Codebase Browser
linux