// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * core.c - DesignWare HS OTG Controller common routines * * Copyright (C) 2004-2013 Synopsys, Inc. */ /* * The Core code provides basic services for accessing and managing the * DWC_otg hardware. These services are used by both the Host Controller * Driver and the Peripheral Controller Driver. */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/spinlock.h> #include <linux/interrupt.h> #include <linux/dma-mapping.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/usb.h> #include <linux/usb/hcd.h> #include <linux/usb/ch11.h> #include "core.h" #include "hcd.h" /** * dwc2_backup_global_registers() - Backup global controller registers. * When suspending usb bus, registers needs to be backuped * if controller power is disabled once suspended. * * @hsotg: Programming view of the DWC_otg controller */ int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) { … } /** * dwc2_restore_global_registers() - Restore controller global registers. * When resuming usb bus, device registers needs to be restored * if controller power were disabled. * * @hsotg: Programming view of the DWC_otg controller */ int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) { … } /** * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down. * * @hsotg: Programming view of the DWC_otg controller * @rem_wakeup: indicates whether resume is initiated by Reset. * @restore: Controller registers need to be restored */ int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, bool restore) { … } /** * dwc2_enter_partial_power_down() - Put controller in Partial Power Down. * * @hsotg: Programming view of the DWC_otg controller */ int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg) { … } /** * dwc2_restore_essential_regs() - Restore essiential regs of core. * * @hsotg: Programming view of the DWC_otg controller * @rmode: Restore mode, enabled in case of remote-wakeup. * @is_host: Host or device mode. */ static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode, int is_host) { … } /** * dwc2_hib_restore_common() - Common part of restore routine. * * @hsotg: Programming view of the DWC_otg controller * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup. * @is_host: Host or device mode. */ void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, int is_host) { … } /** * dwc2_wait_for_mode() - Waits for the controller mode. * @hsotg: Programming view of the DWC_otg controller. * @host_mode: If true, waits for host mode, otherwise device mode. */ static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg, bool host_mode) { … } /** * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce * filter is enabled. * * @hsotg: Programming view of DWC_otg controller */ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) { … } /* * dwc2_enter_hibernation() - Common function to enter hibernation. * * @hsotg: Programming view of the DWC_otg controller * @is_host: True if core is in host mode. * * Return: 0 if successful, negative error code otherwise */ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host) { … } /* * dwc2_exit_hibernation() - Common function to exit from hibernation. * * @hsotg: Programming view of the DWC_otg controller * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup. * @reset: Enabled in case of restore with reset. * @is_host: True if core is in host mode. * * Return: 0 if successful, negative error code otherwise */ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, int reset, int is_host) { … } /* * Do core a soft reset of the core. Be careful with this because it * resets all the internal state machines of the core. */ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait) { … } /** * dwc2_force_mode() - Force the mode of the controller. * * Forcing the mode is needed for two cases: * * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the * controller to stay in a particular mode regardless of ID pin * changes. We do this once during probe. * * 2) During probe we want to read reset values of the hw * configuration registers that are only available in either host or * device mode. We may need to force the mode if the current mode does * not allow us to access the register in the mode that we want. * * In either case it only makes sense to force the mode if the * controller hardware is OTG capable. * * Checks are done in this function to determine whether doing a force * would be valid or not. * * If a force is done, it requires a IDDIG debounce filter delay if * the filter is configured and enabled. We poll the current mode of * the controller to account for this delay. * * @hsotg: Programming view of DWC_otg controller * @host: Host mode flag */ void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) { … } /** * dwc2_clear_force_mode() - Clears the force mode bits. * * After clearing the bits, wait up to 100 ms to account for any * potential IDDIG filter delay. We can't know if we expect this delay * or not because the value of the connector ID status is affected by * the force mode. We only need to call this once during probe if * dr_mode == OTG. * * @hsotg: Programming view of DWC_otg controller */ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) { … } /* * Sets or clears force mode based on the dr_mode parameter. */ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) { … } /* * dwc2_enable_acg - enable active clock gating feature */ void dwc2_enable_acg(struct dwc2_hsotg *hsotg) { … } /** * dwc2_dump_host_registers() - Prints the host registers * * @hsotg: Programming view of DWC_otg controller * * NOTE: This function will be removed once the peripheral controller code * is integrated and the driver is stable */ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) { … } /** * dwc2_dump_global_registers() - Prints the core global registers * * @hsotg: Programming view of DWC_otg controller * * NOTE: This function will be removed once the peripheral controller code * is integrated and the driver is stable */ void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) { … } /** * dwc2_flush_tx_fifo() - Flushes a Tx FIFO * * @hsotg: Programming view of DWC_otg controller * @num: Tx FIFO to flush */ void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) { … } /** * dwc2_flush_rx_fifo() - Flushes the Rx FIFO * * @hsotg: Programming view of DWC_otg controller */ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) { … } bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) { … } /** * dwc2_enable_global_interrupts() - Enables the controller's Global * Interrupt in the AHB Config register * * @hsotg: Programming view of DWC_otg controller */ void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) { … } /** * dwc2_disable_global_interrupts() - Disables the controller's Global * Interrupt in the AHB Config register * * @hsotg: Programming view of DWC_otg controller */ void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) { … } /* Returns the controller's GHWCFG2.OTG_MODE. */ unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg) { … } /* Returns true if the controller is capable of DRD. */ bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) { … } /* Returns true if the controller is host-only. */ bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) { … } /* Returns true if the controller is device-only. */ bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) { … } /** * dwc2_hsotg_wait_bit_set - Waits for bit to be set. * @hsotg: Programming view of DWC_otg controller. * @offset: Register's offset where bit/bits must be set. * @mask: Mask of the bit/bits which must be set. * @timeout: Timeout to wait. * * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout. */ int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, u32 timeout) { … } /** * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear. * @hsotg: Programming view of DWC_otg controller. * @offset: Register's offset where bit/bits must be set. * @mask: Mask of the bit/bits which must be set. * @timeout: Timeout to wait. * * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout. */ int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, u32 timeout) { … } /* * Initializes the FSLSPClkSel field of the HCFG register depending on the * PHY type */ void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) { … } static void dwc2_set_clock_switch_timer(struct dwc2_hsotg *hsotg) { … } static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) { … } static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) { … } static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg) { … } int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) { … } MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;