/* SPDX-License-Identifier: GPL-2.0 */ /* * Driver for the NXP ISP1760 chip * * Copyright 2021 Linaro, Rui Miguel Silva * Copyright 2014 Laurent Pinchart * Copyright 2007 Sebastian Siewior * * Contacts: * Sebastian Siewior <[email protected]> * Laurent Pinchart <[email protected]> * Rui Miguel Silva <[email protected]> */ #ifndef _ISP176x_REGS_H_ #define _ISP176x_REGS_H_ /* ----------------------------------------------------------------------------- * Host Controller */ /* ISP1760/31 */ /* EHCI capability registers */ #define ISP176x_HC_VERSION … #define ISP176x_HC_HCSPARAMS … #define ISP176x_HC_HCCPARAMS … /* EHCI operational registers */ #define ISP176x_HC_USBCMD … #define ISP176x_HC_USBSTS … #define ISP176x_HC_FRINDEX … #define ISP176x_HC_CONFIGFLAG … #define ISP176x_HC_PORTSC1 … #define ISP176x_HC_ISO_PTD_DONEMAP … #define ISP176x_HC_ISO_PTD_SKIPMAP … #define ISP176x_HC_ISO_PTD_LASTPTD … #define ISP176x_HC_INT_PTD_DONEMAP … #define ISP176x_HC_INT_PTD_SKIPMAP … #define ISP176x_HC_INT_PTD_LASTPTD … #define ISP176x_HC_ATL_PTD_DONEMAP … #define ISP176x_HC_ATL_PTD_SKIPMAP … #define ISP176x_HC_ATL_PTD_LASTPTD … /* Configuration Register */ #define ISP176x_HC_HW_MODE_CTRL … #define ISP176x_HC_CHIP_ID … #define ISP176x_HC_SCRATCH … #define ISP176x_HC_RESET … #define ISP176x_HC_BUFFER_STATUS … #define ISP176x_HC_MEMORY … /* Interrupt Register */ #define ISP176x_HC_INTERRUPT … #define ISP176x_HC_INTERRUPT_ENABLE … #define ISP176x_HC_ISO_IRQ_MASK_OR … #define ISP176x_HC_INT_IRQ_MASK_OR … #define ISP176x_HC_ATL_IRQ_MASK_OR … #define ISP176x_HC_ISO_IRQ_MASK_AND … #define ISP176x_HC_INT_IRQ_MASK_AND … #define ISP176x_HC_ATL_IRQ_MASK_AND … #define ISP176x_HC_OTG_CTRL … #define ISP176x_HC_OTG_CTRL_SET … #define ISP176x_HC_OTG_CTRL_CLEAR … enum isp176x_host_controller_fields { … }; /* ISP1763 */ /* EHCI operational registers */ #define ISP1763_HC_USBCMD … #define ISP1763_HC_USBSTS … #define ISP1763_HC_FRINDEX … #define ISP1763_HC_CONFIGFLAG … #define ISP1763_HC_PORTSC1 … #define ISP1763_HC_ISO_PTD_DONEMAP … #define ISP1763_HC_ISO_PTD_SKIPMAP … #define ISP1763_HC_ISO_PTD_LASTPTD … #define ISP1763_HC_INT_PTD_DONEMAP … #define ISP1763_HC_INT_PTD_SKIPMAP … #define ISP1763_HC_INT_PTD_LASTPTD … #define ISP1763_HC_ATL_PTD_DONEMAP … #define ISP1763_HC_ATL_PTD_SKIPMAP … #define ISP1763_HC_ATL_PTD_LASTPTD … /* Configuration Register */ #define ISP1763_HC_HW_MODE_CTRL … #define ISP1763_HC_CHIP_REV … #define ISP1763_HC_CHIP_ID … #define ISP1763_HC_SCRATCH … #define ISP1763_HC_RESET … #define ISP1763_HC_BUFFER_STATUS … #define ISP1763_HC_MEMORY … #define ISP1763_HC_DATA … /* Interrupt Register */ #define ISP1763_HC_INTERRUPT … #define ISP1763_HC_INTERRUPT_ENABLE … #define ISP1763_HC_ISO_IRQ_MASK_OR … #define ISP1763_HC_INT_IRQ_MASK_OR … #define ISP1763_HC_ATL_IRQ_MASK_OR … #define ISP1763_HC_ISO_IRQ_MASK_AND … #define ISP1763_HC_INT_IRQ_MASK_AND … #define ISP1763_HC_ATL_IRQ_MASK_AND … #define ISP1763_HC_OTG_CTRL_SET … #define ISP1763_HC_OTG_CTRL_CLEAR … /* ----------------------------------------------------------------------------- * Peripheral Controller */ #define DC_IEPTX(n) … #define DC_IEPRX(n) … #define DC_IEPRXTX(n) … #define ISP176x_DC_CDBGMOD_ACK … #define ISP176x_DC_DDBGMODIN_ACK … #define ISP176x_DC_DDBGMODOUT_ACK … #define ISP176x_DC_IEP0SETUP … #define ISP176x_DC_IEVBUS … #define ISP176x_DC_IEHS_STA … #define ISP176x_DC_IERESM … #define ISP176x_DC_IESUSP … #define ISP176x_DC_IEBRST … #define ISP176x_HW_OTG_DISABLE_CLEAR … #define ISP176x_HW_SW_SEL_HC_DC_CLEAR … #define ISP176x_HW_VBUS_DRV_CLEAR … #define ISP176x_HW_SEL_CP_EXT_CLEAR … #define ISP176x_HW_DM_PULLDOWN_CLEAR … #define ISP176x_HW_DP_PULLDOWN_CLEAR … #define ISP176x_HW_DP_PULLUP_CLEAR … #define ISP176x_HW_OTG_DISABLE … #define ISP176x_HW_SW_SEL_HC_DC … #define ISP176x_HW_VBUS_DRV … #define ISP176x_HW_SEL_CP_EXT … #define ISP176x_HW_DM_PULLDOWN … #define ISP176x_HW_DP_PULLDOWN … #define ISP176x_HW_DP_PULLUP … #define ISP176x_DC_ENDPTYP_ISOC … #define ISP176x_DC_ENDPTYP_BULK … #define ISP176x_DC_ENDPTYP_INTERRUPT … /* Initialization Registers */ #define ISP176x_DC_ADDRESS … #define ISP176x_DC_MODE … #define ISP176x_DC_INTCONF … #define ISP176x_DC_DEBUG … #define ISP176x_DC_INTENABLE … /* Data Flow Registers */ #define ISP176x_DC_EPMAXPKTSZ … #define ISP176x_DC_EPTYPE … #define ISP176x_DC_BUFLEN … #define ISP176x_DC_BUFSTAT … #define ISP176x_DC_DATAPORT … #define ISP176x_DC_CTRLFUNC … #define ISP176x_DC_EPINDEX … /* DMA Registers */ #define ISP176x_DC_DMACMD … #define ISP176x_DC_DMATXCOUNT … #define ISP176x_DC_DMACONF … #define ISP176x_DC_DMAHW … #define ISP176x_DC_DMAINTREASON … #define ISP176x_DC_DMAINTEN … #define ISP176x_DC_DMAEP … #define ISP176x_DC_DMABURSTCOUNT … /* General Registers */ #define ISP176x_DC_INTERRUPT … #define ISP176x_DC_CHIPID … #define ISP176x_DC_FRAMENUM … #define ISP176x_DC_SCRATCH … #define ISP176x_DC_UNLOCKDEV … #define ISP176x_DC_INTPULSEWIDTH … #define ISP176x_DC_TESTMODE … enum isp176x_device_controller_fields { … }; /* ISP1763 */ /* Initialization Registers */ #define ISP1763_DC_ADDRESS … #define ISP1763_DC_MODE … #define ISP1763_DC_INTCONF … #define ISP1763_DC_INTENABLE … /* Data Flow Registers */ #define ISP1763_DC_EPMAXPKTSZ … #define ISP1763_DC_EPTYPE … #define ISP1763_DC_BUFLEN … #define ISP1763_DC_BUFSTAT … #define ISP1763_DC_DATAPORT … #define ISP1763_DC_CTRLFUNC … #define ISP1763_DC_EPINDEX … /* DMA Registers */ #define ISP1763_DC_DMACMD … #define ISP1763_DC_DMATXCOUNT … #define ISP1763_DC_DMACONF … #define ISP1763_DC_DMAHW … #define ISP1763_DC_DMAINTREASON … #define ISP1763_DC_DMAINTEN … #define ISP1763_DC_DMAEP … #define ISP1763_DC_DMABURSTCOUNT … /* General Registers */ #define ISP1763_DC_INTERRUPT … #define ISP1763_DC_CHIPID_LOW … #define ISP1763_DC_CHIPID_HIGH … #define ISP1763_DC_FRAMENUM … #define ISP1763_DC_SCRATCH … #define ISP1763_DC_UNLOCKDEV … #define ISP1763_DC_INTPULSEWIDTH … #define ISP1763_DC_TESTMODE … #endif
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