/* SPDX-License-Identifier: GPL-2.0 */ /* * USBSS device controller driver header file * * Copyright (C) 2018-2019 Cadence. * Copyright (C) 2017-2018 NXP * * Author: Pawel Laszczak <[email protected]> * Pawel Jez <[email protected]> * Peter Chen <[email protected]> */ #ifndef __LINUX_CDNS3_GADGET #define __LINUX_CDNS3_GADGET #include <linux/usb/gadget.h> #include <linux/dma-direction.h> /* * USBSS-DEV register interface. * This corresponds to the USBSS Device Controller Interface */ /** * struct cdns3_usb_regs - device controller registers. * @usb_conf: Global Configuration. * @usb_sts: Global Status. * @usb_cmd: Global Command. * @usb_itpn: ITP/SOF number. * @usb_lpm: Global Command. * @usb_ien: USB Interrupt Enable. * @usb_ists: USB Interrupt Status. * @ep_sel: Endpoint Select. * @ep_traddr: Endpoint Transfer Ring Address. * @ep_cfg: Endpoint Configuration. * @ep_cmd: Endpoint Command. * @ep_sts: Endpoint Status. * @ep_sts_sid: Endpoint Status. * @ep_sts_en: Endpoint Status Enable. * @drbl: Doorbell. * @ep_ien: EP Interrupt Enable. * @ep_ists: EP Interrupt Status. * @usb_pwr: Global Power Configuration. * @usb_conf2: Global Configuration 2. * @usb_cap1: Capability 1. * @usb_cap2: Capability 2. * @usb_cap3: Capability 3. * @usb_cap4: Capability 4. * @usb_cap5: Capability 5. * @usb_cap6: Capability 6. * @usb_cpkt1: Custom Packet 1. * @usb_cpkt2: Custom Packet 2. * @usb_cpkt3: Custom Packet 3. * @ep_dma_ext_addr: Upper address for DMA operations. * @buf_addr: Address for On-chip Buffer operations. * @buf_data: Data for On-chip Buffer operations. * @buf_ctrl: On-chip Buffer Access Control. * @dtrans: DMA Transfer Mode. * @tdl_from_trb: Source of TD Configuration. * @tdl_beh: TDL Behavior Configuration. * @ep_tdl: Endpoint TDL. * @tdl_beh2: TDL Behavior 2 Configuration. * @dma_adv_td: DMA Advance TD Configuration. * @reserved1: Reserved. * @cfg_regs: Configuration. * @reserved2: Reserved. * @dma_axi_ctrl: AXI Control. * @dma_axi_id: AXI ID register. * @dma_axi_cap: AXI Capability. * @dma_axi_ctrl0: AXI Control 0. * @dma_axi_ctrl1: AXI Control 1. */ struct cdns3_usb_regs { … }; /* USB_CONF - bitmasks */ /* Reset USB device configuration. */ #define USB_CONF_CFGRST … /* Set Configuration. */ #define USB_CONF_CFGSET … /* Disconnect USB device in SuperSpeed. */ #define USB_CONF_USB3DIS … /* Disconnect USB device in HS/FS */ #define USB_CONF_USB2DIS … /* Little Endian access - default */ #define USB_CONF_LENDIAN … /* * Big Endian access. Driver assume that byte order for * SFRs access always is as Little Endian so this bit * is not used. */ #define USB_CONF_BENDIAN … /* Device software reset. */ #define USB_CONF_SWRST … /* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/ #define USB_CONF_DSING … /* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */ #define USB_CONF_DMULT … /* DMA clock turn-off enable. */ #define USB_CONF_DMAOFFEN … /* DMA clock turn-off disable. */ #define USB_CONF_DMAOFFDS … /* Clear Force Full Speed. */ #define USB_CONF_CFORCE_FS … /* Set Force Full Speed. */ #define USB_CONF_SFORCE_FS … /* Device enable. */ #define USB_CONF_DEVEN … /* Device disable. */ #define USB_CONF_DEVDS … /* L1 LPM state entry enable (used in HS/FS mode). */ #define USB_CONF_L1EN … /* L1 LPM state entry disable (used in HS/FS mode). */ #define USB_CONF_L1DS … /* USB 2.0 clock gate disable. */ #define USB_CONF_CLK2OFFEN … /* USB 2.0 clock gate enable. */ #define USB_CONF_CLK2OFFDS … /* L0 LPM state entry request (used in HS/FS mode). */ #define USB_CONF_LGO_L0 … /* USB 3.0 clock gate disable. */ #define USB_CONF_CLK3OFFEN … /* USB 3.0 clock gate enable. */ #define USB_CONF_CLK3OFFDS … /* Bit 23 is reserved*/ /* U1 state entry enable (used in SS mode). */ #define USB_CONF_U1EN … /* U1 state entry disable (used in SS mode). */ #define USB_CONF_U1DS … /* U2 state entry enable (used in SS mode). */ #define USB_CONF_U2EN … /* U2 state entry disable (used in SS mode). */ #define USB_CONF_U2DS … /* U0 state entry request (used in SS mode). */ #define USB_CONF_LGO_U0 … /* U1 state entry request (used in SS mode). */ #define USB_CONF_LGO_U1 … /* U2 state entry request (used in SS mode). */ #define USB_CONF_LGO_U2 … /* SS.Inactive state entry request (used in SS mode) */ #define USB_CONF_LGO_SSINACT … /* USB_STS - bitmasks */ /* * Configuration status. * 1 - device is in the configured state. * 0 - device is not configured. */ #define USB_STS_CFGSTS_MASK … #define USB_STS_CFGSTS(p) … /* * On-chip memory overflow. * 0 - On-chip memory status OK. * 1 - On-chip memory overflow. */ #define USB_STS_OV_MASK … #define USB_STS_OV(p) … /* * SuperSpeed connection status. * 0 - USB in SuperSpeed mode disconnected. * 1 - USB in SuperSpeed mode connected. */ #define USB_STS_USB3CONS_MASK … #define USB_STS_USB3CONS(p) … /* * DMA transfer configuration status. * 0 - single request. * 1 - multiple TRB chain * Supported only for controller version < DEV_VER_V3 */ #define USB_STS_DTRANS_MASK … #define USB_STS_DTRANS(p) … /* * Device speed. * 0 - Undefined (value after reset). * 1 - Low speed * 2 - Full speed * 3 - High speed * 4 - Super speed */ #define USB_STS_USBSPEED_MASK … #define USB_STS_USBSPEED(p) … #define USB_STS_LS … #define USB_STS_FS … #define USB_STS_HS … #define USB_STS_SS … #define DEV_UNDEFSPEED(p) … #define DEV_LOWSPEED(p) … #define DEV_FULLSPEED(p) … #define DEV_HIGHSPEED(p) … #define DEV_SUPERSPEED(p) … /* * Endianness for SFR access. * 0 - Little Endian order (default after hardware reset). * 1 - Big Endian order */ #define USB_STS_ENDIAN_MASK … #define USB_STS_ENDIAN(p) … /* * HS/FS clock turn-off status. * 0 - hsfs clock is always on. * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled * (default after hardware reset). */ #define USB_STS_CLK2OFF_MASK … #define USB_STS_CLK2OFF(p) … /* * PCLK clock turn-off status. * 0 - pclk clock is always on. * 1 - pclk clock turn-off in U3 (SS mode) is enabled * (default after hardware reset). */ #define USB_STS_CLK3OFF_MASK … #define USB_STS_CLK3OFF(p) … /* * Controller in reset state. * 0 - Internal reset is active. * 1 - Internal reset is not active and controller is fully operational. */ #define USB_STS_IN_RST_MASK … #define USB_STS_IN_RST(p) … /* * Status of the "TDL calculation basing on TRB" feature. * 0 - disabled * 1 - enabled * Supported only for DEV_VER_V2 controller version. */ #define USB_STS_TDL_TRB_ENABLED … /* * Device enable Status. * 0 - USB device is disabled (VBUS input is disconnected from internal logic). * 1 - USB device is enabled (VBUS input is connected to the internal logic). */ #define USB_STS_DEVS_MASK … #define USB_STS_DEVS(p) … /* * Address status. * 0 - USB device is default state. * 1 - USB device is at least in address state. */ #define USB_STS_ADDRESSED_MASK … #define USB_STS_ADDRESSED(p) … /* * L1 LPM state enable status (used in HS/FS mode). * 0 - Entering to L1 LPM state disabled. * 1 - Entering to L1 LPM state enabled. */ #define USB_STS_L1ENS_MASK … #define USB_STS_L1ENS(p) … /* * Internal VBUS connection status (used both in HS/FS and SS mode). * 0 - internal VBUS is not detected. * 1 - internal VBUS is detected. */ #define USB_STS_VBUSS_MASK … #define USB_STS_VBUSS(p) … /* * HS/FS LPM state (used in FS/HS mode). * 0 - L0 State * 1 - L1 State * 2 - L2 State * 3 - L3 State */ #define USB_STS_LPMST_MASK … #define DEV_L0_STATE(p) … #define DEV_L1_STATE(p) … #define DEV_L2_STATE(p) … #define DEV_L3_STATE(p) … /* * Disable HS status (used in FS/HS mode). * 0 - the disconnect bit for HS/FS mode is set . * 1 - the disconnect bit for HS/FS mode is not set. */ #define USB_STS_USB2CONS_MASK … #define USB_STS_USB2CONS(p) … /* * HS/FS mode connection status (used in FS/HS mode). * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled. * 1 - High Speed operations in USB2.0 (FS/HS). */ #define USB_STS_DISABLE_HS_MASK … #define USB_STS_DISABLE_HS(p) … /* * U1 state enable status (used in SS mode). * 0 - Entering to U1 state disabled. * 1 - Entering to U1 state enabled. */ #define USB_STS_U1ENS_MASK … #define USB_STS_U1ENS(p) … /* * U2 state enable status (used in SS mode). * 0 - Entering to U2 state disabled. * 1 - Entering to U2 state enabled. */ #define USB_STS_U2ENS_MASK … #define USB_STS_U2ENS(p) … /* * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current * SuperSpeed link state */ #define USB_STS_LST_MASK … #define DEV_LST_U0 … #define DEV_LST_U1 … #define DEV_LST_U2 … #define DEV_LST_U3 … #define DEV_LST_DISABLED … #define DEV_LST_RXDETECT … #define DEV_LST_INACTIVE … #define DEV_LST_POLLING … #define DEV_LST_RECOVERY … #define DEV_LST_HOT_RESET … #define DEV_LST_COMP_MODE … #define DEV_LST_LB_STATE … /* * DMA clock turn-off status. * 0 - DMA clock is always on (default after hardware reset). * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled. */ #define USB_STS_DMAOFF_MASK … #define USB_STS_DMAOFF(p) … /* * SFR Endian status. * 0 - Little Endian order (default after hardware reset). * 1 - Big Endian order. */ #define USB_STS_ENDIAN2_MASK … #define USB_STS_ENDIAN2(p) … /* USB_CMD - bitmasks */ /* Set Function Address */ #define USB_CMD_SET_ADDR … /* * Function Address This field is saved to the device only when the field * SET_ADDR is set '1 ' during write to USB_CMD register. * Software is responsible for entering the address of the device during * SET_ADDRESS request service. This field should be set immediately after * the SETUP packet is decoded, and prior to confirmation of the status phase */ #define USB_CMD_FADDR_MASK … #define USB_CMD_FADDR(p) … /* Send Function Wake Device Notification TP (used only in SS mode). */ #define USB_CMD_SDNFW … /* Set Test Mode (used only in HS/FS mode). */ #define USB_CMD_STMODE … /* Test mode selector (used only in HS/FS mode) */ #define USB_STS_TMODE_SEL_MASK … #define USB_STS_TMODE_SEL(p) … /* * Send Latency Tolerance Message Device Notification TP (used only * in SS mode). */ #define USB_CMD_SDNLTM … /* Send Custom Transaction Packet (used only in SS mode) */ #define USB_CMD_SPKT … /*Device Notification 'Function Wake' - Interface value (only in SS mode. */ #define USB_CMD_DNFW_INT_MASK … #define USB_STS_DNFW_INT(p) … /* * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0] * (used only in SS mode). */ #define USB_CMD_DNLTM_BELT_MASK … #define USB_STS_DNLTM_BELT(p) … /* USB_ITPN - bitmasks */ /* * ITP(SS) / SOF (HS/FS) number * In SS mode this field represent number of last ITP received from host. * In HS/FS mode this field represent number of last SOF received from host. */ #define USB_ITPN_MASK … #define USB_ITPN(p) … /* USB_LPM - bitmasks */ /* Host Initiated Resume Duration. */ #define USB_LPM_HIRD_MASK … #define USB_LPM_HIRD(p) … /* Remote Wakeup Enable (bRemoteWake). */ #define USB_LPM_BRW … /* USB_IEN - bitmasks */ /* SS connection interrupt enable */ #define USB_IEN_CONIEN … /* SS disconnection interrupt enable. */ #define USB_IEN_DISIEN … /* USB SS warm reset interrupt enable. */ #define USB_IEN_UWRESIEN … /* USB SS hot reset interrupt enable */ #define USB_IEN_UHRESIEN … /* SS link U3 state enter interrupt enable (suspend).*/ #define USB_IEN_U3ENTIEN … /* SS link U3 state exit interrupt enable (wakeup). */ #define USB_IEN_U3EXTIEN … /* SS link U2 state enter interrupt enable.*/ #define USB_IEN_U2ENTIEN … /* SS link U2 state exit interrupt enable.*/ #define USB_IEN_U2EXTIEN … /* SS link U1 state enter interrupt enable.*/ #define USB_IEN_U1ENTIEN … /* SS link U1 state exit interrupt enable.*/ #define USB_IEN_U1EXTIEN … /* ITP/SOF packet detected interrupt enable.*/ #define USB_IEN_ITPIEN … /* Wakeup interrupt enable.*/ #define USB_IEN_WAKEIEN … /* Send Custom Packet interrupt enable.*/ #define USB_IEN_SPKTIEN … /* HS/FS mode connection interrupt enable.*/ #define USB_IEN_CON2IEN … /* HS/FS mode disconnection interrupt enable.*/ #define USB_IEN_DIS2IEN … /* USB reset (HS/FS mode) interrupt enable.*/ #define USB_IEN_U2RESIEN … /* LPM L2 state enter interrupt enable.*/ #define USB_IEN_L2ENTIEN … /* LPM L2 state exit interrupt enable.*/ #define USB_IEN_L2EXTIEN … /* LPM L1 state enter interrupt enable.*/ #define USB_IEN_L1ENTIEN … /* LPM L1 state exit interrupt enable.*/ #define USB_IEN_L1EXTIEN … /* Configuration reset interrupt enable.*/ #define USB_IEN_CFGRESIEN … /* Start of the USB SS warm reset interrupt enable.*/ #define USB_IEN_UWRESSIEN … /* End of the USB SS warm reset interrupt enable.*/ #define USB_IEN_UWRESEIEN … #define USB_IEN_INIT … /* USB_ISTS - bitmasks */ /* SS Connection detected. */ #define USB_ISTS_CONI … /* SS Disconnection detected. */ #define USB_ISTS_DISI … /* UUSB warm reset detectede. */ #define USB_ISTS_UWRESI … /* USB hot reset detected. */ #define USB_ISTS_UHRESI … /* U3 link state enter detected (suspend).*/ #define USB_ISTS_U3ENTI … /* U3 link state exit detected (wakeup). */ #define USB_ISTS_U3EXTI … /* U2 link state enter detected.*/ #define USB_ISTS_U2ENTI … /* U2 link state exit detected.*/ #define USB_ISTS_U2EXTI … /* U1 link state enter detected.*/ #define USB_ISTS_U1ENTI … /* U1 link state exit detected.*/ #define USB_ISTS_U1EXTI … /* ITP/SOF packet detected.*/ #define USB_ISTS_ITPI … /* Wakeup detected.*/ #define USB_ISTS_WAKEI … /* Send Custom Packet detected.*/ #define USB_ISTS_SPKTI … /* HS/FS mode connection detected.*/ #define USB_ISTS_CON2I … /* HS/FS mode disconnection detected.*/ #define USB_ISTS_DIS2I … /* USB reset (HS/FS mode) detected.*/ #define USB_ISTS_U2RESI … /* LPM L2 state enter detected.*/ #define USB_ISTS_L2ENTI … /* LPM L2 state exit detected.*/ #define USB_ISTS_L2EXTI … /* LPM L1 state enter detected.*/ #define USB_ISTS_L1ENTI … /* LPM L1 state exit detected.*/ #define USB_ISTS_L1EXTI … /* USB configuration reset detected.*/ #define USB_ISTS_CFGRESI … /* Start of the USB warm reset detected.*/ #define USB_ISTS_UWRESSI … /* End of the USB warm reset detected.*/ #define USB_ISTS_UWRESEI … /* USB_SEL - bitmasks */ #define EP_SEL_EPNO_MASK … /* Endpoint number. */ #define EP_SEL_EPNO(p) … /* Endpoint direction bit - 0 - OUT, 1 - IN. */ #define EP_SEL_DIR … #define select_ep_in(nr) … #define select_ep_out … /* EP_TRADDR - bitmasks */ /* Transfer Ring address. */ #define EP_TRADDR_TRADDR(p) … /* EP_CFG - bitmasks */ /* Endpoint enable */ #define EP_CFG_ENABLE … /* * Endpoint type. * 1 - isochronous * 2 - bulk * 3 - interrupt */ #define EP_CFG_EPTYPE_MASK … #define EP_CFG_EPTYPE(p) … /* Stream support enable (only in SS mode). */ #define EP_CFG_STREAM_EN … /* TDL check (only in SS mode for BULK EP). */ #define EP_CFG_TDL_CHK … /* SID check (only in SS mode for BULK OUT EP). */ #define EP_CFG_SID_CHK … /* DMA transfer endianness. */ #define EP_CFG_EPENDIAN … /* Max burst size (used only in SS mode). */ #define EP_CFG_MAXBURST_MASK … #define EP_CFG_MAXBURST(p) … #define EP_CFG_MAXBURST_MAX … /* ISO max burst. */ #define EP_CFG_MULT_MASK … #define EP_CFG_MULT(p) … #define EP_CFG_MULT_MAX … /* ISO max burst. */ #define EP_CFG_MAXPKTSIZE_MASK … #define EP_CFG_MAXPKTSIZE(p) … /* Max number of buffered packets. */ #define EP_CFG_BUFFERING_MASK … #define EP_CFG_BUFFERING(p) … #define EP_CFG_BUFFERING_MAX … /* EP_CMD - bitmasks */ /* Endpoint reset. */ #define EP_CMD_EPRST … /* Endpoint STALL set. */ #define EP_CMD_SSTALL … /* Endpoint STALL clear. */ #define EP_CMD_CSTALL … /* Send ERDY TP. */ #define EP_CMD_ERDY … /* Request complete. */ #define EP_CMD_REQ_CMPL … /* Transfer descriptor ready. */ #define EP_CMD_DRDY … /* Data flush. */ #define EP_CMD_DFLUSH … /* * Transfer Descriptor Length write (used only for Bulk Stream capable * endpoints in SS mode). * Bit Removed from DEV_VER_V3 controller version. */ #define EP_CMD_STDL … /* * Transfer Descriptor Length (used only in SS mode for bulk endpoints). * Bits Removed from DEV_VER_V3 controller version. */ #define EP_CMD_TDL_MASK … #define EP_CMD_TDL_SET(p) … #define EP_CMD_TDL_GET(p) … #define EP_CMD_TDL_MAX … /* ERDY Stream ID value (used in SS mode). */ #define EP_CMD_ERDY_SID_MASK … #define EP_CMD_ERDY_SID(p) … /* EP_STS - bitmasks */ /* Setup transfer complete. */ #define EP_STS_SETUP … /* Endpoint STALL status. */ #define EP_STS_STALL(p) … /* Interrupt On Complete. */ #define EP_STS_IOC … /* Interrupt on Short Packet. */ #define EP_STS_ISP … /* Transfer descriptor missing. */ #define EP_STS_DESCMIS … /* Stream Rejected (used only in SS mode) */ #define EP_STS_STREAMR … /* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */ #define EP_STS_MD_EXIT … /* TRB error. */ #define EP_STS_TRBERR … /* Not ready (used only in SS mode). */ #define EP_STS_NRDY … /* DMA busy bit. */ #define EP_STS_DBUSY … /* Endpoint Buffer Empty */ #define EP_STS_BUFFEMPTY(p) … /* Current Cycle Status */ #define EP_STS_CCS(p) … /* Prime (used only in SS mode. */ #define EP_STS_PRIME … /* Stream error (used only in SS mode). */ #define EP_STS_SIDERR … /* OUT size mismatch. */ #define EP_STS_OUTSMM … /* ISO transmission error. */ #define EP_STS_ISOERR … /* Host Packet Pending (only for SS mode). */ #define EP_STS_HOSTPP(p) … /* Stream Protocol State Machine State (only for Bulk stream endpoints). */ #define EP_STS_SPSMST_MASK … #define EP_STS_SPSMST_DISABLED(p) … #define EP_STS_SPSMST_IDLE(p) … #define EP_STS_SPSMST_START_STREAM(p) … #define EP_STS_SPSMST_MOVE_DATA(p) … /* Interrupt On Transfer complete. */ #define EP_STS_IOT … /* OUT queue endpoint number. */ #define EP_STS_OUTQ_NO_MASK … #define EP_STS_OUTQ_NO(p) … /* OUT queue valid flag. */ #define EP_STS_OUTQ_VAL_MASK … #define EP_STS_OUTQ_VAL(p) … /* SETUP WAIT. */ #define EP_STS_STPWAIT … /* EP_STS_SID - bitmasks */ /* Stream ID (used only in SS mode). */ #define EP_STS_SID_MASK … #define EP_STS_SID(p) … /* EP_STS_EN - bitmasks */ /* SETUP interrupt enable. */ #define EP_STS_EN_SETUPEN … /* OUT transfer missing descriptor enable. */ #define EP_STS_EN_DESCMISEN … /* Stream Rejected enable. */ #define EP_STS_EN_STREAMREN … /* Move Data Exit enable.*/ #define EP_STS_EN_MD_EXITEN … /* TRB enable. */ #define EP_STS_EN_TRBERREN … /* NRDY enable. */ #define EP_STS_EN_NRDYEN … /* Prime enable. */ #define EP_STS_EN_PRIMEEEN … /* Stream error enable. */ #define EP_STS_EN_SIDERREN … /* OUT size mismatch enable. */ #define EP_STS_EN_OUTSMMEN … /* ISO transmission error enable. */ #define EP_STS_EN_ISOERREN … /* Interrupt on Transmission complete enable. */ #define EP_STS_EN_IOTEN … /* Setup Wait interrupt enable. */ #define EP_STS_EN_STPWAITEN … /* DRBL- bitmasks */ #define DB_VALUE_BY_INDEX(index) … #define DB_VALUE_EP0_OUT … #define DB_VALUE_EP0_IN … /* EP_IEN - bitmasks */ #define EP_IEN(index) … #define EP_IEN_EP_OUT0 … #define EP_IEN_EP_IN0 … /* EP_ISTS - bitmasks */ #define EP_ISTS(index) … #define EP_ISTS_EP_OUT0 … #define EP_ISTS_EP_IN0 … /* USB_PWR- bitmasks */ /*Power Shut Off capability enable*/ #define PUSB_PWR_PSO_EN … /*Power Shut Off capability disable*/ #define PUSB_PWR_PSO_DS … /* * Enables turning-off Reference Clock. * This bit is optional and implemented only when support for OTG is * implemented (indicated by OTG_READY bit set to '1'). */ #define PUSB_PWR_STB_CLK_SWITCH_EN … /* * Status bit indicating that operation required by STB_CLK_SWITCH_EN write * is completed */ #define PUSB_PWR_STB_CLK_SWITCH_DONE … /* This bit informs if Fast Registers Access is enabled. */ #define PUSB_PWR_FST_REG_ACCESS_STAT … /* Fast Registers Access Enable. */ #define PUSB_PWR_FST_REG_ACCESS … /* USB_CONF2- bitmasks */ /* * Writing 1 disables TDL calculation basing on TRB feature in controller * for DMULT mode. * Bit supported only for DEV_VER_V2 version. */ #define USB_CONF2_DIS_TDL_TRB … /* * Writing 1 enables TDL calculation basing on TRB feature in controller * for DMULT mode. * Bit supported only for DEV_VER_V2 version. */ #define USB_CONF2_EN_TDL_TRB … /* USB_CAP1- bitmasks */ /* * SFR Interface type * These field reflects type of SFR interface implemented: * 0x0 - OCP * 0x1 - AHB, * 0x2 - PLB * 0x3 - AXI * 0x4-0xF - reserved */ #define USB_CAP1_SFR_TYPE_MASK … #define DEV_SFR_TYPE_OCP(p) … #define DEV_SFR_TYPE_AHB(p) … #define DEV_SFR_TYPE_PLB(p) … #define DEV_SFR_TYPE_AXI(p) … /* * SFR Interface width * These field reflects width of SFR interface implemented: * 0x0 - 8 bit interface, * 0x1 - 16 bit interface, * 0x2 - 32 bit interface * 0x3 - 64 bit interface * 0x4-0xF - reserved */ #define USB_CAP1_SFR_WIDTH_MASK … #define DEV_SFR_WIDTH_8(p) … #define DEV_SFR_WIDTH_16(p) … #define DEV_SFR_WIDTH_32(p) … #define DEV_SFR_WIDTH_64(p) … /* * DMA Interface type * These field reflects type of DMA interface implemented: * 0x0 - OCP * 0x1 - AHB, * 0x2 - PLB * 0x3 - AXI * 0x4-0xF - reserved */ #define USB_CAP1_DMA_TYPE_MASK … #define DEV_DMA_TYPE_OCP(p) … #define DEV_DMA_TYPE_AHB(p) … #define DEV_DMA_TYPE_PLB(p) … #define DEV_DMA_TYPE_AXI(p) … /* * DMA Interface width * These field reflects width of DMA interface implemented: * 0x0 - reserved, * 0x1 - reserved, * 0x2 - 32 bit interface * 0x3 - 64 bit interface * 0x4-0xF - reserved */ #define USB_CAP1_DMA_WIDTH_MASK … #define DEV_DMA_WIDTH_32(p) … #define DEV_DMA_WIDTH_64(p) … /* * USB3 PHY Interface type * These field reflects type of USB3 PHY interface implemented: * 0x0 - USB PIPE, * 0x1 - RMMI, * 0x2-0xF - reserved */ #define USB_CAP1_U3PHY_TYPE_MASK … #define DEV_U3PHY_PIPE(p) … #define DEV_U3PHY_RMMI(p) … /* * USB3 PHY Interface width * These field reflects width of USB3 PHY interface implemented: * 0x0 - 8 bit PIPE interface, * 0x1 - 16 bit PIPE interface, * 0x2 - 32 bit PIPE interface, * 0x3 - 64 bit PIPE interface * 0x4-0xF - reserved * Note: When SSIC interface is implemented this field shows the width of * internal PIPE interface. The RMMI interface is always 20bit wide. */ #define USB_CAP1_U3PHY_WIDTH_MASK … #define DEV_U3PHY_WIDTH_8(p) … #define DEV_U3PHY_WIDTH_16(p) … #define DEV_U3PHY_WIDTH_32(p) … #define DEV_U3PHY_WIDTH_64(p) … /* * USB2 PHY Interface enable * These field informs if USB2 PHY interface is implemented: * 0x0 - interface NOT implemented, * 0x1 - interface implemented */ #define USB_CAP1_U2PHY_EN(p) … /* * USB2 PHY Interface type * These field reflects type of USB2 PHY interface implemented: * 0x0 - UTMI, * 0x1 - ULPI */ #define DEV_U2PHY_ULPI(p) … /* * USB2 PHY Interface width * These field reflects width of USB2 PHY interface implemented: * 0x0 - 8 bit interface, * 0x1 - 16 bit interface, * Note: The ULPI interface is always 8bit wide. */ #define DEV_U2PHY_WIDTH_16(p) … /* * OTG Ready * 0x0 - pure device mode * 0x1 - some features and ports for CDNS USB OTG controller are implemented. */ #define USB_CAP1_OTG_READY(p) … /* * When set, indicates that controller supports automatic internal TDL * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode * Supported only for DEV_VER_V2 controller version. */ #define USB_CAP1_TDL_FROM_TRB(p) … /* USB_CAP2- bitmasks */ /* * The actual size of the connected On-chip RAM memory in kB: * - 0 means 256 kB (max supported mem size) * - value other than 0 reflects the mem size in kB */ #define USB_CAP2_ACTUAL_MEM_SIZE(p) … /* * Max supported mem size * These field reflects width of on-chip RAM address bus width, * which determines max supported mem size: * 0x0-0x7 - reserved, * 0x8 - support for 4kB mem, * 0x9 - support for 8kB mem, * 0xA - support for 16kB mem, * 0xB - support for 32kB mem, * 0xC - support for 64kB mem, * 0xD - support for 128kB mem, * 0xE - support for 256kB mem, * 0xF - reserved */ #define USB_CAP2_MAX_MEM_SIZE(p) … /* USB_CAP3- bitmasks */ #define EP_IS_IMPLEMENTED(reg, index) … /* USB_CAP4- bitmasks */ #define EP_SUPPORT_ISO(reg, index) … /* USB_CAP5- bitmasks */ #define EP_SUPPORT_STREAM(reg, index) … /* USB_CAP6- bitmasks */ /* The USBSS-DEV Controller Internal build number. */ #define GET_DEV_BASE_VERSION(p) … /* The USBSS-DEV Controller version number. */ #define GET_DEV_CUSTOM_VERSION(p) … #define DEV_VER_NXP_V1 … #define DEV_VER_TI_V1 … #define DEV_VER_V2 … #define DEV_VER_V3 … /* DBG_LINK1- bitmasks */ /* * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum * time required for decoding the received LFPS as an LFPS.U1_Exit. */ #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) … /* * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for * phytxelecidle deassertion when LFPS.U1_Exit */ #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK … #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) … /* * RXDET_BREAK_DIS value This parameter configures terminating the Far-end * Receiver termination detection sequence: * 0: it is possible that USBSS_DEV will terminate Farend receiver * termination detection sequence * 1: USBSS_DEV will not terminate Far-end receiver termination * detection sequence */ #define DBG_LINK1_RXDET_BREAK_DIS … /* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */ #define DBG_LINK1_LFPS_GEN_PING(p) … /* * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically * cleared. Writing '0' has no effect */ #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET … /* * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically * cleared. Writing '0' has no effect */ #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET … /* * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes * the RXDET_BREAK_DIS field value to the device. This bit is automatically * cleared. Writing '0' has no effect */ #define DBG_LINK1_RXDET_BREAK_DIS_SET … /* * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes * the LFPS_GEN_PING field value to the device. This bit is automatically * cleared. Writing '0' has no effect." */ #define DBG_LINK1_LFPS_GEN_PING_SET … /* DMA_AXI_CTRL- bitmasks */ /* The mawprot pin configuration. */ #define DMA_AXI_CTRL_MARPROT(p) … /* The marprot pin configuration. */ #define DMA_AXI_CTRL_MAWPROT(p) … #define DMA_AXI_CTRL_NON_SECURE … #define gadget_to_cdns3_device(g) … #define ep_to_cdns3_ep(ep) … /*-------------------------------------------------------------------------*/ /* * USBSS-DEV DMA interface. */ #define TRBS_PER_SEGMENT … #define ISO_MAX_INTERVAL … #define MAX_TRB_LENGTH … #if TRBS_PER_SEGMENT < 2 #error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2." #endif #define TRBS_PER_STREAM_SEGMENT … #if TRBS_PER_STREAM_SEGMENT < 2 #error "Incorrect TRBS_PER_STREAMS_SEGMENT. Minimal Transfer Ring size is 2." #endif /* *Only for ISOC endpoints - maximum number of TRBs is calculated as * pow(2, bInterval-1) * number of usb requests. It is limitation made by * driver to save memory. Controller must prepare TRB for each ITP even * if bInterval > 1. It's the reason why driver needs so many TRBs for * isochronous endpoints. */ #define TRBS_PER_ISOC_SEGMENT … #define GET_TRBS_PER_SEGMENT(ep_type) … /** * struct cdns3_trb - represent Transfer Descriptor block. * @buffer: pointer to buffer data * @length: length of data * @control: control flags. * * This structure describes transfer block serviced by DMA module. */ struct cdns3_trb { … }; #define TRB_SIZE … #define TRB_RING_SIZE … #define TRB_STREAM_RING_SIZE … #define TRB_ISO_RING_SIZE … #define TRB_CTRL_RING_SIZE … /* TRB bit mask */ #define TRB_TYPE_BITMASK … #define TRB_TYPE(p) … #define TRB_FIELD_TO_TYPE(p) … /* TRB type IDs */ /* bulk, interrupt, isoc , and control data stage */ #define TRB_NORMAL … /* TRB for linking ring segments */ #define TRB_LINK … /* Cycle bit - indicates TRB ownership by driver or hw*/ #define TRB_CYCLE … /* * When set to '1', the device will toggle its interpretation of the Cycle bit */ #define TRB_TOGGLE … /* * The controller will set it if OUTSMM (OUT size mismatch) is detected, * this bit is for normal TRB */ #define TRB_SMM … /* * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was * processed while USB short packet was received. No more buffers defined by * the TD will be used. DMA will automatically advance to next TD. * - Shall be set to 0 by Software when putting TRB on the Transfer Ring * - Shall be set to 1 by Controller when Short Packet condition for this TRB * is detected independent if ISP is set or not. */ #define TRB_SP … /* Interrupt on short packet*/ #define TRB_ISP … /*Setting this bit enables FIFO DMA operation mode*/ #define TRB_FIFO_MODE … /* Set PCIe no snoop attribute */ #define TRB_CHAIN … /* Interrupt on completion */ #define TRB_IOC … /* stream ID bitmasks. */ #define TRB_STREAM_ID_BITMASK … #define TRB_STREAM_ID(p) … #define TRB_FIELD_TO_STREAMID(p) … /* Size of TD expressed in USB packets for HS/FS mode. */ #define TRB_TDL_HS_SIZE(p) … #define TRB_TDL_HS_SIZE_GET(p) … /* transfer_len bitmasks. */ #define TRB_LEN(p) … /* Size of TD expressed in USB packets for SS mode. */ #define TRB_TDL_SS_SIZE(p) … #define TRB_TDL_SS_SIZE_GET(p) … /* transfer_len bitmasks - bits 31:24 */ #define TRB_BURST_LEN(p) … #define TRB_BURST_LEN_GET(p) … /* Data buffer pointer bitmasks*/ #define TRB_BUFFER(p) … /*-------------------------------------------------------------------------*/ /* Driver numeric constants */ /* Such declaration should be added to ch9.h */ #define USB_DEVICE_MAX_ADDRESS … /* Endpoint init values */ #define CDNS3_EP_MAX_PACKET_LIMIT … #define CDNS3_EP_MAX_STREAMS … #define CDNS3_EP0_MAX_PACKET_LIMIT … /* All endpoints including EP0 */ #define CDNS3_ENDPOINTS_MAX_COUNT … #define CDNS3_EP_ZLP_BUF_SIZE … #define CDNS3_MAX_NUM_DESCMISS_BUF … #define CDNS3_DESCMIS_BUF_SIZE … #define CDNS3_WA2_NUM_BUFFERS … /*-------------------------------------------------------------------------*/ /* Used structs */ struct cdns3_device; /** * struct cdns3_endpoint - extended device side representation of USB endpoint. * @endpoint: usb endpoint * @pending_req_list: list of requests queuing on transfer ring. * @deferred_req_list: list of requests waiting for queuing on transfer ring. * @wa2_descmiss_req_list: list of requests internally allocated by driver. * @trb_pool: transfer ring - array of transaction buffers * @trb_pool_dma: dma address of transfer ring * @cdns3_dev: device associated with this endpoint * @name: a human readable name e.g. ep1out * @flags: specify the current state of endpoint * @descmis_req: internal transfer object used for getting data from on-chip * buffer. It can happen only if function driver doesn't send usb_request * object on time. * @dir: endpoint direction * @num: endpoint number (1 - 15) * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK * @interval: interval between packets used for ISOC endpoint. * @free_trbs: number of free TRBs in transfer ring * @num_trbs: number of all TRBs in transfer ring * @alloc_ring_size: size of the allocated TRB ring * @pcs: producer cycle state * @ccs: consumer cycle state * @enqueue: enqueue index in transfer ring * @dequeue: dequeue index in transfer ring * @trb_burst_size: number of burst used in trb. */ struct cdns3_endpoint { … }; /** * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer * @buf: aligned to 8 bytes data buffer. Buffer address used in * TRB shall be aligned to 8. * @dma: dma address * @size: size of buffer * @in_use: inform if this buffer is associated with usb_request * @list: used to adding instance of this object to list */ struct cdns3_aligned_buf { … }; /** * struct cdns3_request - extended device side representation of usb_request * object . * @request: generic usb_request object describing single I/O request. * @priv_ep: extended representation of usb_ep object * @trb: the first TRB association with this request * @start_trb: number of the first TRB in transfer ring * @end_trb: number of the last TRB in transfer ring * @aligned_buf: object holds information about aligned buffer associated whit * this endpoint * @flags: flag specifying special usage of request * @list: used by internally allocated request to add to wa2_descmiss_req_list. * @finished_trb: number of trb has already finished per request * @num_of_trb: how many trbs in this request */ struct cdns3_request { … }; #define to_cdns3_request(r) … /*Stages used during enumeration process.*/ #define CDNS3_SETUP_STAGE … #define CDNS3_DATA_STAGE … #define CDNS3_STATUS_STAGE … /** * struct cdns3_device - represent USB device. * @dev: pointer to device structure associated whit this controller * @sysdev: pointer to the DMA capable device * @gadget: device side representation of the peripheral controller * @gadget_driver: pointer to the gadget driver * @dev_ver: device controller version. * @lock: for synchronizing * @regs: base address for device side registers * @setup_buf: used while processing usb control requests * @setup_dma: dma address for setup_buf * @zlp_buf - zlp buffer * @ep0_stage: ep0 stage during enumeration process. * @ep0_data_dir: direction for control transfer * @eps: array of pointers to all endpoints with exclusion ep0 * @aligned_buf_list: list of aligned buffers internally allocated by driver * @aligned_buf_wq: workqueue freeing no longer used aligned buf. * @selected_ep: actually selected endpoint. It's used only to improve * performance. * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP. * @u1_allowed: allow device transition to u1 state * @u2_allowed: allow device transition to u2 state * @is_selfpowered: device is self powered * @setup_pending: setup packet is processing by gadget driver * @hw_configured_flag: hardware endpoint configuration was set. * @wake_up_flag: allow device to remote up the host * @status_completion_no_call: indicate that driver is waiting for status s * stage completion. It's used in deferred SET_CONFIGURATION request. * @onchip_buffers: number of available on-chip buffers. * @onchip_used_size: actual size of on-chip memory assigned to endpoints. * @pending_status_wq: workqueue handling status stage for deferred requests. * @pending_status_request: request for which status stage was deferred */ struct cdns3_device { … }; void cdns3_set_register_bit(void __iomem *ptr, u32 mask); dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep, struct cdns3_trb *trb); enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev); void cdns3_pending_setup_status_handler(struct work_struct *work); void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev); void cdns3_set_hw_configuration(struct cdns3_device *priv_dev); void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep); void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable); struct usb_request *cdns3_next_request(struct list_head *list); void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm); int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep); u8 cdns3_ep_addr_to_index(u8 ep_addr); int cdns3_gadget_ep_set_wedge(struct usb_ep *ep); int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value); void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep); int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep); struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags); void cdns3_gadget_ep_free_request(struct usb_ep *ep, struct usb_request *request); int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request); void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep, struct cdns3_request *priv_req, int status); int cdns3_init_ep0(struct cdns3_device *priv_dev, struct cdns3_endpoint *priv_ep); void cdns3_ep0_config(struct cdns3_device *priv_dev); int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable); void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir); int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev); #endif /* __LINUX_CDNS3_GADGET */
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