/* SPDX-License-Identifier: GPL-2.0 */ /* * xHCI host controller driver * * Copyright (C) 2008 Intel Corp. * * Author: Sarah Sharp * Some code borrowed from the Linux EHCI driver. */ /* HC should halt within 16 ms, but use 32 ms as some hosts take longer */ #define XHCI_MAX_HALT_USEC … /* HC not running - set to 1 when run/stop bit is cleared. */ #define XHCI_STS_HALT … /* HCCPARAMS offset from PCI base address */ #define XHCI_HCC_PARAMS_OFFSET … /* HCCPARAMS contains the first extended capability pointer */ #define XHCI_HCC_EXT_CAPS(p) … /* Command and Status registers offset from the Operational Registers address */ #define XHCI_CMD_OFFSET … #define XHCI_STS_OFFSET … #define XHCI_MAX_EXT_CAPS … /* Capability Register */ /* bits 7:0 - how long is the Capabilities register */ #define XHCI_HC_LENGTH(p) … /* Extended capability register fields */ #define XHCI_EXT_CAPS_ID(p) … #define XHCI_EXT_CAPS_NEXT(p) … #define XHCI_EXT_CAPS_VAL(p) … /* Extended capability IDs - ID 0 reserved */ #define XHCI_EXT_CAPS_LEGACY … #define XHCI_EXT_CAPS_PROTOCOL … #define XHCI_EXT_CAPS_PM … #define XHCI_EXT_CAPS_VIRT … #define XHCI_EXT_CAPS_ROUTE … /* IDs 6-9 reserved */ #define XHCI_EXT_CAPS_DEBUG … /* Vendor caps */ #define XHCI_EXT_CAPS_VENDOR_INTEL … /* USB Legacy Support Capability - section 7.1.1 */ #define XHCI_HC_BIOS_OWNED … #define XHCI_HC_OS_OWNED … /* USB Legacy Support Capability - section 7.1.1 */ /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ #define XHCI_LEGACY_SUPPORT_OFFSET … /* USB Legacy Support Control and Status Register - section 7.1.2 */ /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ #define XHCI_LEGACY_CONTROL_OFFSET … /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ #define XHCI_LEGACY_DISABLE_SMI … #define XHCI_LEGACY_SMI_EVENTS … /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ #define XHCI_L1C … /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ #define XHCI_HLC … #define XHCI_BLC … /* command register values to disable interrupts and halt the HC */ /* start/stop HC execution - do not write unless HC is halted*/ #define XHCI_CMD_RUN … /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ #define XHCI_CMD_EIE … /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ #define XHCI_CMD_HSEIE … /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ #define XHCI_CMD_EWE … #define XHCI_IRQS … /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ #define XHCI_STS_CNR … /** * struct xhci_protocol_caps * @revision: major revision, minor revision, capability ID, * and next capability pointer. * @name_string: Four ASCII characters to say which spec this xHC * follows, typically "USB ". * @port_info: Port offset, count, and protocol-defined information. */ struct xhci_protocol_caps { … }; #define XHCI_EXT_PORT_MAJOR(x) … #define XHCI_EXT_PORT_MINOR(x) … #define XHCI_EXT_PORT_PSIC(x) … #define XHCI_EXT_PORT_OFF(x) … #define XHCI_EXT_PORT_COUNT(x) … #define XHCI_EXT_PORT_PSIV(x) … #define XHCI_EXT_PORT_PSIE(x) … #define XHCI_EXT_PORT_PLT(x) … #define XHCI_EXT_PORT_PFD(x) … #define XHCI_EXT_PORT_LP(x) … #define XHCI_EXT_PORT_PSIM(x) … #include <linux/io.h> /** * Find the offset of the extended capabilities with capability ID id. * * @base PCI MMIO registers base address. * @start address at which to start looking, (0 or HCC_PARAMS to start at * beginning of list) * @id Extended capability ID to search for, or 0 for the next * capability * * Returns the offset of the next matching extended capability structure. * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL, * and this provides a way to find them all. */ static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id) { … }
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