// SPDX-License-Identifier: GPL-2.0+ /* * Faraday FOTG210 USB OTG controller * * Copyright (C) 2013 Faraday Technology Corporation * Author: Yuan-Hsin Chen <[email protected]> */ #include <linux/kernel.h> #define FOTG210_MAX_NUM_EP … #define FOTG210_MAX_FIFO_NUM … /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */ #define FOTG210_GMIR … #define GMIR_INT_POLARITY … #define GMIR_MHC_INT … #define GMIR_MOTG_INT … #define GMIR_MDEV_INT … /* Device Main Control Register(0x100) */ #define FOTG210_DMCR … #define DMCR_HS_EN … #define DMCR_CHIP_EN … #define DMCR_SFRST … #define DMCR_GOSUSP … #define DMCR_GLINT_EN … #define DMCR_HALF_SPEED … #define DMCR_CAP_RMWAKUP … /* Device Address Register(0x104) */ #define FOTG210_DAR … #define DAR_AFT_CONF … /* Device Test Register(0x108) */ #define FOTG210_DTR … #define DTR_TST_CLRFF … /* PHY Test Mode Selector register(0x114) */ #define FOTG210_PHYTMSR … #define PHYTMSR_TST_PKT … #define PHYTMSR_TST_SE0NAK … #define PHYTMSR_TST_KSTA … #define PHYTMSR_TST_JSTA … #define PHYTMSR_UNPLUG … /* Cx configuration and FIFO Empty Status register(0x120) */ #define FOTG210_DCFESR … #define DCFESR_FIFO_EMPTY(fifo) … #define DCFESR_CX_EMP … #define DCFESR_CX_CLR … #define DCFESR_CX_STL … #define DCFESR_TST_PKDONE … #define DCFESR_CX_DONE … /* Device IDLE Counter Register(0x124) */ #define FOTG210_DICR … /* Device Mask of Interrupt Group Register (0x130) */ #define FOTG210_DMIGR … #define DMIGR_MINT_G2 … #define DMIGR_MINT_G1 … #define DMIGR_MINT_G0 … /* Device Mask of Interrupt Source Group 0(0x134) */ #define FOTG210_DMISGR0 … #define DMISGR0_MCX_COMEND … #define DMISGR0_MCX_OUT_INT … #define DMISGR0_MCX_IN_INT … #define DMISGR0_MCX_SETUP_INT … /* Device Mask of Interrupt Source Group 1 Register(0x138)*/ #define FOTG210_DMISGR1 … #define DMISGR1_MF3_IN_INT … #define DMISGR1_MF2_IN_INT … #define DMISGR1_MF1_IN_INT … #define DMISGR1_MF0_IN_INT … #define DMISGR1_MF_IN_INT(fifo) … #define DMISGR1_MF3_SPK_INT … #define DMISGR1_MF3_OUT_INT … #define DMISGR1_MF2_SPK_INT … #define DMISGR1_MF2_OUT_INT … #define DMISGR1_MF1_SPK_INT … #define DMISGR1_MF1_OUT_INT … #define DMISGR1_MF0_SPK_INT … #define DMISGR1_MF0_OUT_INT … #define DMISGR1_MF_OUTSPK_INT(fifo) … /* Device Mask of Interrupt Source Group 2 Register (0x13C) */ #define FOTG210_DMISGR2 … #define DMISGR2_MDMA_ERROR … #define DMISGR2_MDMA_CMPLT … /* Device Interrupt group Register (0x140) */ #define FOTG210_DIGR … #define DIGR_INT_G2 … #define DIGR_INT_G1 … #define DIGR_INT_G0 … /* Device Interrupt Source Group 0 Register (0x144) */ #define FOTG210_DISGR0 … #define DISGR0_CX_COMABT_INT … #define DISGR0_CX_COMFAIL_INT … #define DISGR0_CX_COMEND_INT … #define DISGR0_CX_OUT_INT … #define DISGR0_CX_IN_INT … #define DISGR0_CX_SETUP_INT … /* Device Interrupt Source Group 1 Register (0x148) */ #define FOTG210_DISGR1 … #define DISGR1_OUT_INT(fifo) … #define DISGR1_SPK_INT(fifo) … #define DISGR1_IN_INT(fifo) … /* Device Interrupt Source Group 2 Register (0x14C) */ #define FOTG210_DISGR2 … #define DISGR2_DMA_ERROR … #define DISGR2_DMA_CMPLT … #define DISGR2_RX0BYTE_INT … #define DISGR2_TX0BYTE_INT … #define DISGR2_ISO_SEQ_ABORT_INT … #define DISGR2_ISO_SEQ_ERR_INT … #define DISGR2_RESM_INT … #define DISGR2_SUSP_INT … #define DISGR2_USBRST_INT … /* Device Receive Zero-Length Data Packet Register (0x150)*/ #define FOTG210_RX0BYTE … #define RX0BYTE_EP8 … #define RX0BYTE_EP7 … #define RX0BYTE_EP6 … #define RX0BYTE_EP5 … #define RX0BYTE_EP4 … #define RX0BYTE_EP3 … #define RX0BYTE_EP2 … #define RX0BYTE_EP1 … /* Device Transfer Zero-Length Data Packet Register (0x154)*/ #define FOTG210_TX0BYTE … #define TX0BYTE_EP8 … #define TX0BYTE_EP7 … #define TX0BYTE_EP6 … #define TX0BYTE_EP5 … #define TX0BYTE_EP4 … #define TX0BYTE_EP3 … #define TX0BYTE_EP2 … #define TX0BYTE_EP1 … /* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */ #define FOTG210_INEPMPSR(ep) … #define INOUTEPMPSR_MPS(mps) … #define INOUTEPMPSR_STL_EP … #define INOUTEPMPSR_RESET_TSEQ … /* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */ #define FOTG210_OUTEPMPSR(ep) … /* Device Endpoint 1~4 Map Register (0x1A0) */ #define FOTG210_EPMAP … #define EPMAP_FIFONO(ep, dir) … #define EPMAP_FIFONOMSK(ep, dir) … /* Device FIFO Map Register (0x1A8) */ #define FOTG210_FIFOMAP … #define FIFOMAP_DIROUT(fifo) … #define FIFOMAP_DIRIN(fifo) … #define FIFOMAP_BIDIR(fifo) … #define FIFOMAP_NA(fifo) … #define FIFOMAP_EPNO(ep) … #define FIFOMAP_EPNOMSK(ep) … /* Device FIFO Confuguration Register (0x1AC) */ #define FOTG210_FIFOCF … #define FIFOCF_TYPE(type, fifo) … #define FIFOCF_BLK_SIN(fifo) … #define FIFOCF_BLK_DUB(fifo) … #define FIFOCF_BLK_TRI(fifo) … #define FIFOCF_BLKSZ_512(fifo) … #define FIFOCF_BLKSZ_1024(fifo) … #define FIFOCF_FIFO_EN(fifo) … /* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */ #define FOTG210_FIBCR(fifo) … #define FIBCR_BCFX … #define FIBCR_FFRST … /* Device DMA Target FIFO Number Register (0x1C0) */ #define FOTG210_DMATFNR … #define DMATFNR_ACC_CXF … #define DMATFNR_ACC_F3 … #define DMATFNR_ACC_F2 … #define DMATFNR_ACC_F1 … #define DMATFNR_ACC_F0 … #define DMATFNR_ACC_FN(fifo) … #define DMATFNR_DISDMA … /* Device DMA Controller Parameter setting 1 Register (0x1C8) */ #define FOTG210_DMACPSR1 … #define DMACPSR1_DMA_LEN(len) … #define DMACPSR1_DMA_ABORT … #define DMACPSR1_DMA_TYPE(dir_in) … #define DMACPSR1_DMA_START … /* Device DMA Controller Parameter setting 2 Register (0x1CC) */ #define FOTG210_DMACPSR2 … /* Device DMA Controller Parameter setting 3 Register (0x1CC) */ #define FOTG210_CXPORT … struct fotg210_request { … }; struct fotg210_ep { … }; struct fotg210_udc { … }; #define gadget_to_fotg210(g) …
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