/* SPDX-License-Identifier: GPL-1.0+ */ /* * OHCI HCD (Host Controller Driver) for USB. * * (C) Copyright 1999 Roman Weissgaerber <[email protected]> * (C) Copyright 2000-2002 David Brownell <[email protected]> * * This file is licenced under the GPL. */ /* * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the * host controller implementation. */ __hc32; __hc16; /* * OHCI Endpoint Descriptor (ED) ... holds TD queue * See OHCI spec, section 4.2 * * This is a "Queue Head" for those transfers, which is why * both EHCI and UHCI call similar structures a "QH". */ struct ed { … } __attribute__ ((aligned …)); #define ED_MASK … /* * OHCI Transfer Descriptor (TD) ... one per transfer segment * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt) * and 4.3.2 (iso) */ struct td { … } __attribute__ ((aligned …)); /* c/b/i need 16; only iso needs 32 */ #define TD_MASK … /* * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW */ #define TD_CC_NOERROR … #define TD_CC_CRC … #define TD_CC_BITSTUFFING … #define TD_CC_DATATOGGLEM … #define TD_CC_STALL … #define TD_DEVNOTRESP … #define TD_PIDCHECKFAIL … #define TD_UNEXPECTEDPID … #define TD_DATAOVERRUN … #define TD_DATAUNDERRUN … /* 0x0A, 0x0B reserved for hardware */ #define TD_BUFFEROVERRUN … #define TD_BUFFERUNDERRUN … /* 0x0E, 0x0F reserved for HCD */ #define TD_NOTACCESSED … /* map OHCI TD status codes (CC) to errno values */ static const int __maybe_unused cc_to_error [16] = …; /* * The HCCA (Host Controller Communications Area) is a 256 byte * structure defined section 4.4.1 of the OHCI spec. The HC is * told the base address of it. It must be 256-byte aligned. */ struct ohci_hcca { … } __attribute__ ((aligned …)); /* * This is the structure of the OHCI controller's memory mapped I/O region. * You must use readl() and writel() (in <asm/io.h>) to access these fields!! * Layout is in section 7 (and appendix B) of the spec. */ struct ohci_regs { … } __attribute__ ((aligned …)); /* OHCI CONTROL AND STATUS REGISTER MASKS */ /* * HcControl (control) register masks */ #define OHCI_CTRL_CBSR … #define OHCI_CTRL_PLE … #define OHCI_CTRL_IE … #define OHCI_CTRL_CLE … #define OHCI_CTRL_BLE … #define OHCI_CTRL_HCFS … #define OHCI_CTRL_IR … #define OHCI_CTRL_RWC … #define OHCI_CTRL_RWE … /* pre-shifted values for HCFS */ #define OHCI_USB_RESET … #define OHCI_USB_RESUME … #define OHCI_USB_OPER … #define OHCI_USB_SUSPEND … /* * HcCommandStatus (cmdstatus) register masks */ #define OHCI_HCR … #define OHCI_CLF … #define OHCI_BLF … #define OHCI_OCR … #define OHCI_SOC … /* * masks used with interrupt registers: * HcInterruptStatus (intrstatus) * HcInterruptEnable (intrenable) * HcInterruptDisable (intrdisable) */ #define OHCI_INTR_SO … #define OHCI_INTR_WDH … #define OHCI_INTR_SF … #define OHCI_INTR_RD … #define OHCI_INTR_UE … #define OHCI_INTR_FNO … #define OHCI_INTR_RHSC … #define OHCI_INTR_OC … #define OHCI_INTR_MIE … /* OHCI ROOT HUB REGISTER MASKS */ /* roothub.portstatus [i] bits */ #define RH_PS_CCS … #define RH_PS_PES … #define RH_PS_PSS … #define RH_PS_POCI … #define RH_PS_PRS … #define RH_PS_PPS … #define RH_PS_LSDA … #define RH_PS_CSC … #define RH_PS_PESC … #define RH_PS_PSSC … #define RH_PS_OCIC … #define RH_PS_PRSC … /* roothub.status bits */ #define RH_HS_LPS … #define RH_HS_OCI … #define RH_HS_DRWE … #define RH_HS_LPSC … #define RH_HS_OCIC … #define RH_HS_CRWE … /* roothub.b masks */ #define RH_B_DR … #define RH_B_PPCM … /* roothub.a masks */ #define RH_A_NDP … #define RH_A_PSM … #define RH_A_NPS … #define RH_A_DT … #define RH_A_OCPM … #define RH_A_NOCP … #define RH_A_POTPGT … /* hcd-private per-urb state */ urb_priv_t; #define TD_HASH_SIZE … // sizeof (struct td) ~= 64 == 2^6 ... #define TD_HASH_FUNC(td_dma) … /* * This is the full ohci controller description * * Note how the "proper" USB information is just * a subset of what the full implementation needs. (Linus) */ enum ohci_rh_state { … }; struct ohci_hcd { … }; #ifdef CONFIG_USB_PCI static inline int quirk_nec(struct ohci_hcd *ohci) { … } static inline int quirk_zfmicro(struct ohci_hcd *ohci) { … } static inline int quirk_amdiso(struct ohci_hcd *ohci) { … } static inline int quirk_amdprefetch(struct ohci_hcd *ohci) { … } #else static inline int quirk_nec(struct ohci_hcd *ohci) { return 0; } static inline int quirk_zfmicro(struct ohci_hcd *ohci) { return 0; } static inline int quirk_amdiso(struct ohci_hcd *ohci) { return 0; } static inline int quirk_amdprefetch(struct ohci_hcd *ohci) { return 0; } #endif /* convert between an hcd pointer and the corresponding ohci_hcd */ static inline struct ohci_hcd *hcd_to_ohci (struct usb_hcd *hcd) { … } static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci) { … } /*-------------------------------------------------------------------------*/ #define ohci_dbg(ohci, fmt, args...) … #define ohci_err(ohci, fmt, args...) … #define ohci_info(ohci, fmt, args...) … #define ohci_warn(ohci, fmt, args...) … /*-------------------------------------------------------------------------*/ /* * While most USB host controllers implement their registers and * in-memory communication descriptors in little-endian format, * a minority (notably the IBM STB04XXX and the Motorola MPC5200 * processors) implement them in big endian format. * * In addition some more exotic implementations like the Toshiba * Spider (aka SCC) cell southbridge are "mixed" endian, that is, * they have a different endianness for registers vs. in-memory * descriptors. * * This attempts to support either format at compile time without a * runtime penalty, or both formats with the additional overhead * of checking a flag bit. * * That leads to some tricky Kconfig rules howevber. There are * different defaults based on some arch/ppc platforms, though * the basic rules are: * * Controller type Kconfig options needed * --------------- ---------------------- * little endian CONFIG_USB_OHCI_LITTLE_ENDIAN * * fully big endian CONFIG_USB_OHCI_BIG_ENDIAN_DESC _and_ * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO * * mixed endian CONFIG_USB_OHCI_LITTLE_ENDIAN _and_ * CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC} * * (If you have a mixed endian controller, you -must- also define * CONFIG_USB_OHCI_LITTLE_ENDIAN or things will not work when building * both your mixed endian and a fully big endian controller support in * the same kernel image). */ #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN #define big_endian_desc … #else #define big_endian_desc … #endif #else #define big_endian_desc(ohci) … #endif #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN #define big_endian_mmio … #else #define big_endian_mmio … #endif #else #define big_endian_mmio(ohci) … #endif /* * Big-endian read/write functions are arch-specific. * Other arches can be added if/when they're needed. * */ static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci, __hc32 __iomem * regs) { … } static inline void _ohci_writel (const struct ohci_hcd *ohci, const unsigned int val, __hc32 __iomem *regs) { … } #define ohci_readl(o,r) … #define ohci_writel(o,v,r) … /*-------------------------------------------------------------------------*/ /* cpu to ohci */ static inline __hc16 cpu_to_hc16 (const struct ohci_hcd *ohci, const u16 x) { … } static inline __hc16 cpu_to_hc16p (const struct ohci_hcd *ohci, const u16 *x) { … } static inline __hc32 cpu_to_hc32 (const struct ohci_hcd *ohci, const u32 x) { … } static inline __hc32 cpu_to_hc32p (const struct ohci_hcd *ohci, const u32 *x) { … } /* ohci to cpu */ static inline u16 hc16_to_cpu (const struct ohci_hcd *ohci, const __hc16 x) { … } static inline u16 hc16_to_cpup (const struct ohci_hcd *ohci, const __hc16 *x) { … } static inline u32 hc32_to_cpu (const struct ohci_hcd *ohci, const __hc32 x) { … } static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x) { … } /*-------------------------------------------------------------------------*/ /* * The HCCA frame number is 16 bits, but is accessed as 32 bits since not all * hardware handles 16 bit reads. Depending on the SoC implementation, the * frame number can wind up in either bits [31:16] (default) or * [15:0] (OHCI_QUIRK_FRAME_NO) on big endian hosts. * * Somewhat similarly, the 16-bit PSW fields in a transfer descriptor are * reordered on BE. */ static inline u16 ohci_frame_no(const struct ohci_hcd *ohci) { … } static inline __hc16 *ohci_hwPSWp(const struct ohci_hcd *ohci, const struct td *td, int index) { … } static inline u16 ohci_hwPSW(const struct ohci_hcd *ohci, const struct td *td, int index) { … } /*-------------------------------------------------------------------------*/ #define FI … #define FSMP(fi) … #define FIT … #define LSTHRESH … static inline void periodic_reinit (struct ohci_hcd *ohci) { … } /* AMD-756 (D2 rev) reports corrupt register contents in some cases. * The erratum (#4) description is incorrect. AMD's workaround waits * till some bits (mostly reserved) are clear; ok for all revs. */ #define read_roothub(hc, register, mask) … static inline u32 roothub_a (struct ohci_hcd *hc) { … } static inline u32 roothub_b (struct ohci_hcd *hc) { … } static inline u32 roothub_status (struct ohci_hcd *hc) { … } static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i) { … } /* Declarations of things exported for use by ohci platform drivers */ struct ohci_driver_overrides { … }; extern void ohci_init_driver(struct hc_driver *drv, const struct ohci_driver_overrides *over); extern int ohci_restart(struct ohci_hcd *ohci); extern int ohci_setup(struct usb_hcd *hcd); extern int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup); extern int ohci_resume(struct usb_hcd *hcd, bool hibernated); extern int ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength); extern int ohci_hub_status_data(struct usb_hcd *hcd, char *buf);
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