/* SPDX-License-Identifier: GPL-2.0 */ /* * ISP1362 HCD (Host Controller Driver) for USB. * * COPYRIGHT (C) by L. Wassmann <[email protected]> */ /* ------------------------------------------------------------------------- */ #define MAX_ROOT_PORTS … #define USE_32BIT … /* These options are mutually exclusive */ #define USE_PLATFORM_DELAY … #define USE_NDELAY … #define DUMMY_DELAY_ACCESS … /* ------------------------------------------------------------------------- */ #define USB_RESET_WIDTH … #define MAX_XFER_SIZE … /* Buffer sizes */ #define ISP1362_BUF_SIZE … #define ISP1362_ISTL_BUFSIZE … #define ISP1362_INTL_BLKSIZE … #define ISP1362_INTL_BUFFERS … #define ISP1362_ATL_BLKSIZE … #define ISP1362_REG_WRITE_OFFSET … #define REG_WIDTH_16 … #define REG_WIDTH_32 … #define REG_WIDTH_MASK … #define REG_NO_MASK … #ifdef ISP1362_DEBUG typedef const unsigned int isp1362_reg_t; #define REG_ACCESS_R … #define REG_ACCESS_W … #define REG_ACCESS_RW … #define REG_ACCESS_MASK … #define ISP1362_REG_NO … #define ISP1362_REG … #define REG_ACCESS_TEST … #define REG_WIDTH_TEST … #else isp1362_reg_t; #define ISP1362_REG_NO(r) … #define ISP1362_REG(name, addr, width, rw) … #define REG_ACCESS_TEST(r) … #define REG_WIDTH_TEST(r, w) … #endif /* OHCI compatible registers */ /* * Note: Some of the ISP1362 'OHCI' registers implement only * a subset of the bits defined in the OHCI spec. * * Bitmasks for the individual bits of these registers are defined in "ohci.h" */ ISP1362_REG(HCREVISION, 0x00, REG_WIDTH_32, REG_ACCESS_R); ISP1362_REG(HCCONTROL, 0x01, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCCMDSTAT, 0x02, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCINTSTAT, 0x03, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCINTENB, 0x04, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCINTDIS, 0x05, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCFMINTVL, 0x0d, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCFMREM, 0x0e, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCFMNUM, 0x0f, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCLSTHRESH, 0x11, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCRHDESCA, 0x12, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCRHDESCB, 0x13, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCRHSTATUS, 0x14, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCRHPORT1, 0x15, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCRHPORT2, 0x16, REG_WIDTH_32, REG_ACCESS_RW); /* Philips ISP1362 specific registers */ ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16, REG_ACCESS_RW); #define HCHWCFG_DISABLE_SUSPEND … #define HCHWCFG_GLOBAL_PWRDOWN … #define HCHWCFG_PULLDOWN_DS2 … #define HCHWCFG_PULLDOWN_DS1 … #define HCHWCFG_CLKNOTSTOP … #define HCHWCFG_ANALOG_OC … #define HCHWCFG_ONEINT … #define HCHWCFG_DACK_MODE … #define HCHWCFG_ONEDMA … #define HCHWCFG_DACK_POL … #define HCHWCFG_DREQ_POL … #define HCHWCFG_DBWIDTH_MASK … #define HCHWCFG_DBWIDTH(n) … #define HCHWCFG_INT_POL … #define HCHWCFG_INT_TRIGGER … #define HCHWCFG_INT_ENABLE … ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16, REG_ACCESS_RW); #define HCDMACFG_CTR_ENABLE … #define HCDMACFG_BURST_LEN_MASK … #define HCDMACFG_BURST_LEN(n) … #define HCDMACFG_BURST_LEN_1 … #define HCDMACFG_BURST_LEN_4 … #define HCDMACFG_BURST_LEN_8 … #define HCDMACFG_DMA_ENABLE … #define HCDMACFG_BUF_TYPE_MASK … #define HCDMACFG_BUF_TYPE(n) … #define HCDMACFG_BUF_ISTL0 … #define HCDMACFG_BUF_ISTL1 … #define HCDMACFG_BUF_INTL … #define HCDMACFG_BUF_ATL … #define HCDMACFG_BUF_DIRECT … #define HCDMACFG_DMA_RW_SELECT … ISP1362_REG(HCXFERCTR, 0x22, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16, REG_ACCESS_RW); #define HCuPINT_SOF … #define HCuPINT_ISTL0 … #define HCuPINT_ISTL1 … #define HCuPINT_EOT … #define HCuPINT_OPR … #define HCuPINT_SUSP … #define HCuPINT_CLKRDY … #define HCuPINT_INTL … #define HCuPINT_ATL … #define HCuPINT_OTG … ISP1362_REG(HCuPINTENB, 0x25, REG_WIDTH_16, REG_ACCESS_RW); /* same bit definitions apply as for HCuPINT */ ISP1362_REG(HCCHIPID, 0x27, REG_WIDTH_16, REG_ACCESS_R); #define HCCHIPID_MASK … #define HCCHIPID_MAGIC … ISP1362_REG(HCSCRATCH, 0x28, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCSWRES, 0x29, REG_WIDTH_16, REG_ACCESS_W); #define HCSWRES_MAGIC … ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_16, REG_ACCESS_RW); #define HCBUFSTAT_ISTL0_FULL … #define HCBUFSTAT_ISTL1_FULL … #define HCBUFSTAT_INTL_ACTIVE … #define HCBUFSTAT_ATL_ACTIVE … #define HCBUFSTAT_RESET_HWPP … #define HCBUFSTAT_ISTL0_ACTIVE … #define HCBUFSTAT_ISTL1_ACTIVE … #define HCBUFSTAT_ISTL0_DONE … #define HCBUFSTAT_ISTL1_DONE … #define HCBUFSTAT_PAIRED_PTDPP … ISP1362_REG(HCDIRADDR, 0x32, REG_WIDTH_32, REG_ACCESS_RW); #define HCDIRADDR_ADDR_MASK … #define HCDIRADDR_ADDR(n) … #define HCDIRADDR_COUNT_MASK … #define HCDIRADDR_COUNT(n) … ISP1362_REG(HCDIRDATA, 0x45, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCISTLBUFSZ, 0x30, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCISTL0PORT, 0x40, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCISTL1PORT, 0x42, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCISTLRATE, 0x47, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCINTLBUFSZ, 0x33, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCINTLPORT, 0x43, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCINTLBLKSZ, 0x53, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCINTLDONE, 0x17, REG_WIDTH_32, REG_ACCESS_R); ISP1362_REG(HCINTLSKIP, 0x18, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCINTLLAST, 0x19, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCINTLCURR, 0x1a, REG_WIDTH_16, REG_ACCESS_R); ISP1362_REG(HCATLBUFSZ, 0x34, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCATLPORT, 0x44, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCATLBLKSZ, 0x54, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCATLDONE, 0x1b, REG_WIDTH_32, REG_ACCESS_R); ISP1362_REG(HCATLSKIP, 0x1c, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCATLLAST, 0x1d, REG_WIDTH_32, REG_ACCESS_RW); ISP1362_REG(HCATLCURR, 0x1e, REG_WIDTH_16, REG_ACCESS_R); ISP1362_REG(HCATLDTC, 0x51, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(OTGCONTROL, 0x62, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(OTGSTATUS, 0x67, REG_WIDTH_16, REG_ACCESS_R); ISP1362_REG(OTGINT, 0x68, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(OTGINTENB, 0x69, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(OTGTIMER, 0x6A, REG_WIDTH_16, REG_ACCESS_RW); ISP1362_REG(OTGALTTMR, 0x6C, REG_WIDTH_16, REG_ACCESS_RW); /* Philips transfer descriptor, cpu-endian */ struct ptd { … } __attribute__ ((packed, aligned …)); #define PTD_HEADER_SIZE … /* ------------------------------------------------------------------------- */ /* Copied from ohci.h: */ /* * Hardware transfer status codes -- CC from PTD */ #define PTD_CC_NOERROR … #define PTD_CC_CRC … #define PTD_CC_BITSTUFFING … #define PTD_CC_DATATOGGLEM … #define PTD_CC_STALL … #define PTD_DEVNOTRESP … #define PTD_PIDCHECKFAIL … #define PTD_UNEXPECTEDPID … #define PTD_DATAOVERRUN … #define PTD_DATAUNDERRUN … /* 0x0A, 0x0B reserved for hardware */ #define PTD_BUFFEROVERRUN … #define PTD_BUFFERUNDERRUN … /* 0x0E, 0x0F reserved for HCD */ #define PTD_NOTACCESSED … /* map OHCI TD status codes (CC) to errno values */ static const int cc_to_error[16] = …; /* * HcControl (control) register masks */ #define OHCI_CTRL_HCFS … #define OHCI_CTRL_RWC … #define OHCI_CTRL_RWE … /* pre-shifted values for HCFS */ #define OHCI_USB_RESET … #define OHCI_USB_RESUME … #define OHCI_USB_OPER … #define OHCI_USB_SUSPEND … /* * HcCommandStatus (cmdstatus) register masks */ #define OHCI_HCR … #define OHCI_SOC … /* * masks used with interrupt registers: * HcInterruptStatus (intrstatus) * HcInterruptEnable (intrenable) * HcInterruptDisable (intrdisable) */ #define OHCI_INTR_SO … #define OHCI_INTR_WDH … #define OHCI_INTR_SF … #define OHCI_INTR_RD … #define OHCI_INTR_UE … #define OHCI_INTR_FNO … #define OHCI_INTR_RHSC … #define OHCI_INTR_OC … #define OHCI_INTR_MIE … /* roothub.portstatus [i] bits */ #define RH_PS_CCS … #define RH_PS_PES … #define RH_PS_PSS … #define RH_PS_POCI … #define RH_PS_PRS … #define RH_PS_PPS … #define RH_PS_LSDA … #define RH_PS_CSC … #define RH_PS_PESC … #define RH_PS_PSSC … #define RH_PS_OCIC … #define RH_PS_PRSC … /* roothub.status bits */ #define RH_HS_LPS … #define RH_HS_OCI … #define RH_HS_DRWE … #define RH_HS_LPSC … #define RH_HS_OCIC … #define RH_HS_CRWE … /* roothub.b masks */ #define RH_B_DR … #define RH_B_PPCM … /* roothub.a masks */ #define RH_A_NDP … #define RH_A_PSM … #define RH_A_NPS … #define RH_A_DT … #define RH_A_OCPM … #define RH_A_NOCP … #define RH_A_POTPGT … #define FI … #define FSMP(fi) … #define LSTHRESH … /* ------------------------------------------------------------------------- */ /* PTD accessor macros. */ #define PTD_GET_COUNT(p) … #define PTD_COUNT(v) … #define PTD_GET_TOGGLE(p) … #define PTD_TOGGLE(v) … #define PTD_GET_ACTIVE(p) … #define PTD_ACTIVE(v) … #define PTD_GET_CC(p) … #define PTD_CC(v) … #define PTD_GET_MPS(p) … #define PTD_MPS(v) … #define PTD_GET_SPD(p) … #define PTD_SPD(v) … #define PTD_GET_LAST(p) … #define PTD_LAST(v) … #define PTD_GET_EP(p) … #define PTD_EP(v) … #define PTD_GET_LEN(p) … #define PTD_LEN(v) … #define PTD_GET_DIR(p) … #define PTD_DIR(v) … #define PTD_GET_FA(p) … #define PTD_FA(v) … #define PTD_GET_SF_INT(p) … #define PTD_SF_INT(v) … #define PTD_GET_SF_ISO(p) … #define PTD_SF_ISO(v) … #define PTD_GET_PR(p) … #define PTD_PR(v) … #define LOG2_PERIODIC_SIZE … #define PERIODIC_SIZE … struct isp1362_ep { … }; struct isp1362_ep_queue { … }; struct isp1362_hcd { … }; static inline const char *ISP1362_INT_NAME(int n) { … } static inline void ALIGNSTAT(struct isp1362_hcd *isp1362_hcd, void *ptr) { … } static inline struct isp1362_hcd *hcd_to_isp1362_hcd(struct usb_hcd *hcd) { … } static inline struct usb_hcd *isp1362_hcd_to_hcd(struct isp1362_hcd *isp1362_hcd) { … } #define frame_before(f1, f2) … /* * ISP1362 HW Interface */ #define DBG(level, fmt...) … #ifdef VERBOSE #define VDBG … #else #define VDBG(fmt...) … #endif #ifdef REGISTERS #define RDBG … #else #define RDBG(fmt...) … #endif #ifdef URB_TRACE #define URB_DBG … #else #define URB_DBG(fmt...) … #endif #if USE_PLATFORM_DELAY #if USE_NDELAY #error USE_PLATFORM_DELAY and USE_NDELAY defined simultaneously. #endif #define isp1362_delay … #elif USE_NDELAY #define isp1362_delay … #else #define isp1362_delay(h, d) … #endif #define get_urb(ep) … /* basic access functions for ISP1362 chip registers */ /* NOTE: The contents of the address pointer register cannot be read back! The driver must ensure, * that all register accesses are performed with interrupts disabled, since the interrupt * handler has no way of restoring the previous state. */ static void isp1362_write_addr(struct isp1362_hcd *isp1362_hcd, isp1362_reg_t reg) { … } static void isp1362_write_data16(struct isp1362_hcd *isp1362_hcd, u16 val) { … } static u16 isp1362_read_data16(struct isp1362_hcd *isp1362_hcd) { … } static void isp1362_write_data32(struct isp1362_hcd *isp1362_hcd, u32 val) { … } static u32 isp1362_read_data32(struct isp1362_hcd *isp1362_hcd) { … } /* use readsw/writesw to access the fifo whenever possible */ /* assume HCDIRDATA or XFERCTR & addr_reg have been set up */ static void isp1362_read_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len) { … } static void isp1362_write_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len) { … } #define isp1362_read_reg16(d, r) … #define isp1362_read_reg32(d, r) … #define isp1362_write_reg16(d, r, v) … #define isp1362_write_reg32(d, r, v) … #define isp1362_set_mask16(d, r, m) … #define isp1362_clr_mask16(d, r, m) … #define isp1362_set_mask32(d, r, m) … #define isp1362_clr_mask32(d, r, m) … #define isp1362_show_reg(d, r) … static void isp1362_write_diraddr(struct isp1362_hcd *isp1362_hcd, u16 offset, u16 len) { … } static void isp1362_read_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len) { … } static void isp1362_write_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len) { … } static void __attribute__((unused)) dump_data(char *buf, int len) { … } #if defined(PTD_TRACE) static void dump_ptd(struct ptd *ptd) { DBG(0, "EP %p: CC=%x EP=%d DIR=%x CNT=%d LEN=%d MPS=%d TGL=%x ACT=%x FA=%d SPD=%x SF=%x PR=%x LST=%x\n", container_of(ptd, struct isp1362_ep, ptd), PTD_GET_CC(ptd), PTD_GET_EP(ptd), PTD_GET_DIR(ptd), PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd), PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd), PTD_GET_FA(ptd), PTD_GET_SPD(ptd), PTD_GET_SF_INT(ptd), PTD_GET_PR(ptd), PTD_GET_LAST(ptd)); DBG(0, " %04x %04x %04x %04x\n", ptd->count, ptd->mps, ptd->len, ptd->faddr); } static void dump_ptd_out_data(struct ptd *ptd, u8 *buf) { if (dbg_level > 0) { if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) { DBG(0, "--out->\n"); dump_data(buf, PTD_GET_LEN(ptd)); } } } static void dump_ptd_in_data(struct ptd *ptd, u8 *buf) { if (dbg_level > 0) { if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) { DBG(0, "<--in--\n"); dump_data(buf, PTD_GET_COUNT(ptd)); } DBG(0, "-----\n"); } } static void dump_ptd_queue(struct isp1362_ep_queue *epq) { struct isp1362_ep *ep; int dbg = dbg_level; dbg_level = 1; list_for_each_entry(ep, &epq->active, active) { dump_ptd(&ep->ptd); dump_data(ep->data, ep->length); } dbg_level = dbg; } #else #define dump_ptd(ptd) … #define dump_ptd_in_data(ptd, buf) … #define dump_ptd_out_data(ptd, buf) … #define dump_ptd_data(ptd, buf) … #define dump_ptd_queue(epq) … #endif
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