/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __LINUX_UHCI_HCD_H #define __LINUX_UHCI_HCD_H #include <linux/list.h> #include <linux/usb.h> #include <linux/clk.h> #define usb_packetid(pipe) … #define PIPE_DEVEP_MASK … /* * Universal Host Controller Interface data structures and defines */ /* Command register */ #define USBCMD … #define USBCMD_RS … #define USBCMD_HCRESET … #define USBCMD_GRESET … #define USBCMD_EGSM … #define USBCMD_FGR … #define USBCMD_SWDBG … #define USBCMD_CF … #define USBCMD_MAXP … /* Status register */ #define USBSTS … #define USBSTS_USBINT … #define USBSTS_ERROR … #define USBSTS_RD … #define USBSTS_HSE … #define USBSTS_HCPE … #define USBSTS_HCH … /* Interrupt enable register */ #define USBINTR … #define USBINTR_TIMEOUT … #define USBINTR_RESUME … #define USBINTR_IOC … #define USBINTR_SP … #define USBFRNUM … #define USBFLBASEADD … #define USBSOF … #define USBSOF_DEFAULT … /* USB port status and control registers */ #define USBPORTSC1 … #define USBPORTSC2 … #define USBPORTSC3 … #define USBPORTSC4 … #define USBPORTSC_CCS … #define USBPORTSC_CSC … #define USBPORTSC_PE … #define USBPORTSC_PEC … #define USBPORTSC_DPLUS … #define USBPORTSC_DMINUS … #define USBPORTSC_RD … #define USBPORTSC_RES1 … #define USBPORTSC_LSDA … #define USBPORTSC_PR … /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */ #define USBPORTSC_OC … #define USBPORTSC_OCC … #define USBPORTSC_SUSP … #define USBPORTSC_RES2 … #define USBPORTSC_RES3 … #define USBPORTSC_RES4 … /* PCI legacy support register */ #define USBLEGSUP … #define USBLEGSUP_DEFAULT … #define USBLEGSUP_RWC … #define USBLEGSUP_RO … /* PCI Intel-specific resume-enable register */ #define USBRES_INTEL … #define USBPORT1EN … #define USBPORT2EN … #define UHCI_PTR_BITS(uhci) … #define UHCI_PTR_TERM(uhci) … #define UHCI_PTR_QH(uhci) … #define UHCI_PTR_DEPTH(uhci) … #define UHCI_PTR_BREADTH(uhci) … #define UHCI_NUMFRAMES … #define UHCI_MAX_SOF_NUMBER … #define CAN_SCHEDULE_FRAMES … #define MAX_PHASE … /* When no queues need Full-Speed Bandwidth Reclamation, * delay this long before turning FSBR off */ #define FSBR_OFF_DELAY … /* If a queue hasn't advanced after this much time, assume it is stuck */ #define QH_WAIT_TIMEOUT … /* * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to * __leXX (normally) or __beXX (given UHCI_BIG_ENDIAN_DESC), depending on * the host controller implementation. * * To facilitate the strongest possible byte-order checking from "sparse" * and so on, we use __leXX unless that's not practical. */ #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC typedef __u32 __bitwise __hc32; typedef __u16 __bitwise __hc16; #else #define __hc32 … #define __hc16 … #endif /* * Queue Headers */ /* * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes * with each endpoint, and qh->element (updated by the HC) is either: * - the next unprocessed TD in the endpoint's queue, or * - UHCI_PTR_TERM (when there's no more traffic for this endpoint). * * The other role of a QH is to serve as a "skeleton" framelist entry, so we * can easily splice a QH for some endpoint into the schedule at the right * place. Then qh->element is UHCI_PTR_TERM. * * In the schedule, qh->link maintains a list of QHs seen by the HC: * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ... * * qh->node is the software equivalent of qh->link. The differences * are that the software list is doubly-linked and QHs in the UNLINKING * state are on the software list but not the hardware schedule. * * For bookkeeping purposes we maintain QHs even for Isochronous endpoints, * but they never get added to the hardware schedule. */ #define QH_STATE_IDLE … #define QH_STATE_UNLINKING … #define QH_STATE_ACTIVE … struct uhci_qh { … } __attribute__((aligned …)); /* * We need a special accessor for the element pointer because it is * subject to asynchronous updates by the controller. */ #define qh_element(qh) … #define LINK_TO_QH(uhci, qh) … /* * Transfer Descriptors */ /* * for TD <status>: */ #define TD_CTRL_SPD … #define TD_CTRL_C_ERR_MASK … #define TD_CTRL_C_ERR_SHIFT … #define TD_CTRL_LS … #define TD_CTRL_IOS … #define TD_CTRL_IOC … #define TD_CTRL_ACTIVE … #define TD_CTRL_STALLED … #define TD_CTRL_DBUFERR … #define TD_CTRL_BABBLE … #define TD_CTRL_NAK … #define TD_CTRL_CRCTIMEO … #define TD_CTRL_BITSTUFF … #define TD_CTRL_ACTLEN_MASK … #define uhci_maxerr(err) … #define uhci_status_bits(ctrl_sts) … #define uhci_actual_length(ctrl_sts) … /* * for TD <info>: (a.k.a. Token) */ #define td_token(uhci, td) … #define TD_TOKEN_DEVADDR_SHIFT … #define TD_TOKEN_TOGGLE_SHIFT … #define TD_TOKEN_TOGGLE … #define TD_TOKEN_EXPLEN_SHIFT … #define TD_TOKEN_EXPLEN_MASK … #define TD_TOKEN_PID_MASK … #define uhci_explen(len) … #define uhci_expected_length(token) … #define uhci_toggle(token) … #define uhci_endpoint(token) … #define uhci_devaddr(token) … #define uhci_devep(token) … #define uhci_packetid(token) … #define uhci_packetout(token) … #define uhci_packetin(token) … /* * The documentation says "4 words for hardware, 4 words for software". * * That's silly, the hardware doesn't care. The hardware only cares that * the hardware words are 16-byte aligned, and we can have any amount of * sw space after the TD entry. * * td->link points to either another TD (not necessarily for the same urb or * even the same endpoint), or nothing (PTR_TERM), or a QH. */ struct uhci_td { … } __attribute__((aligned …)); /* * We need a special accessor for the control/status word because it is * subject to asynchronous updates by the controller. */ #define td_status(uhci, td) … #define LINK_TO_TD(uhci, td) … /* * Skeleton Queue Headers */ /* * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for * automatic queuing. To make it easy to insert entries into the schedule, * we have a skeleton of QHs for each predefined Interrupt latency. * Asynchronous QHs (low-speed control, full-speed control, and bulk) * go onto the period-1 interrupt list, since they all get accessed on * every frame. * * When we want to add a new QH, we add it to the list starting from the * appropriate skeleton QH. For instance, the schedule can look like this: * * skel int128 QH * dev 1 interrupt QH * dev 5 interrupt QH * skel int64 QH * skel int32 QH * ... * skel int1 + async QH * dev 5 low-speed control QH * dev 1 bulk QH * dev 2 bulk QH * * There is a special terminating QH used to keep full-speed bandwidth * reclamation active when no full-speed control or bulk QHs are linked * into the schedule. It has an inactive TD (to work around a PIIX bug, * see the Intel errata) and it points back to itself. * * There's a special skeleton QH for Isochronous QHs which never appears * on the schedule. Isochronous TDs go on the schedule before the * skeleton QHs. The hardware accesses them directly rather than * through their QH, which is used only for bookkeeping purposes. * While the UHCI spec doesn't forbid the use of QHs for Isochronous, * it doesn't use them either. And the spec says that queues never * advance on an error completion status, which makes them totally * unsuitable for Isochronous transfers. * * There's also a special skeleton QH used for QHs which are in the process * of unlinking and so may still be in use by the hardware. It too never * appears on the schedule. */ #define UHCI_NUM_SKELQH … #define SKEL_UNLINK … #define skel_unlink_qh … #define SKEL_ISO … #define skel_iso_qh … /* int128, int64, ..., int1 = 2, 3, ..., 9 */ #define SKEL_INDEX(exponent) … #define SKEL_ASYNC … #define skel_async_qh … #define SKEL_TERM … #define skel_term_qh … /* The following entries refer to sublists of skel_async_qh */ #define SKEL_LS_CONTROL … #define SKEL_FS_CONTROL … #define SKEL_FSBR … #define SKEL_BULK … /* * The UHCI controller and root hub */ /* * States for the root hub: * * To prevent "bouncing" in the presence of electrical noise, * when there are no devices attached we delay for 1 second in the * RUNNING_NODEVS state before switching to the AUTO_STOPPED state. * * (Note that the AUTO_STOPPED state won't be necessary once the hub * driver learns to autosuspend.) */ enum uhci_rh_state { … }; /* * The full UHCI controller information: */ struct uhci_hcd { … }; /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd) { … } static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci) { … } #define uhci_dev(u) … /* Utility macro for comparing frame numbers */ #define uhci_frame_before_eq(f1, f2) … /* * Private per-URB data */ struct urb_priv { … }; /* Some special IDs */ #define PCI_VENDOR_ID_GENESYS … #define PCI_DEVICE_ID_GL880S_UHCI … /* Aspeed SoC needs some quirks */ static inline bool uhci_is_aspeed(const struct uhci_hcd *uhci) { … } /* * Functions used to access controller registers. The UCHI spec says that host * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts * we use memory mapped registers. */ #ifdef CONFIG_HAS_IOPORT #define UHCI_IN … #define UHCI_OUT … #else #define UHCI_IN … #define UHCI_OUT … #endif #ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC /* Support PCI only */ static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) { … } static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) { … } static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) { … } static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) { … } static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) { … } static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) { … } #else /* Support non-PCI host controllers */ #if defined(CONFIG_USB_PCI) && defined(HAS_IOPORT) /* Support PCI and non-PCI host controllers */ #define uhci_has_pci_registers … #else /* Support non-PCI host controllers only */ #define uhci_has_pci_registers … #endif #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO /* Support (non-PCI) big endian host controllers */ #define uhci_big_endian_mmio … #else #define uhci_big_endian_mmio … #endif static inline int uhci_aspeed_reg(unsigned int reg) { switch (reg) { case USBCMD: return 00; case USBSTS: return 0x04; case USBINTR: return 0x08; case USBFRNUM: return 0x80; case USBFLBASEADD: return 0x0c; case USBSOF: return 0x84; case USBPORTSC1: return 0x88; case USBPORTSC2: return 0x8c; case USBPORTSC3: return 0x90; case USBPORTSC4: return 0x94; default: pr_warn("UHCI: Unsupported register 0x%02x on Aspeed\n", reg); /* Return an unimplemented register */ return 0x10; } } static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) { if (uhci_has_pci_registers(uhci)) return UHCI_IN(inl(uhci->io_addr + reg)); else if (uhci_is_aspeed(uhci)) return readl(uhci->regs + uhci_aspeed_reg(reg)); #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO else if (uhci_big_endian_mmio(uhci)) return readl_be(uhci->regs + reg); #endif else return readl(uhci->regs + reg); } static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) { if (uhci_has_pci_registers(uhci)) UHCI_OUT(outl(val, uhci->io_addr + reg)); else if (uhci_is_aspeed(uhci)) writel(val, uhci->regs + uhci_aspeed_reg(reg)); #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO else if (uhci_big_endian_mmio(uhci)) writel_be(val, uhci->regs + reg); #endif else writel(val, uhci->regs + reg); } static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) { if (uhci_has_pci_registers(uhci)) return UHCI_IN(inw(uhci->io_addr + reg)); else if (uhci_is_aspeed(uhci)) return readl(uhci->regs + uhci_aspeed_reg(reg)); #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO else if (uhci_big_endian_mmio(uhci)) return readw_be(uhci->regs + reg); #endif else return readw(uhci->regs + reg); } static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) { if (uhci_has_pci_registers(uhci)) UHCI_OUT(outw(val, uhci->io_addr + reg)); else if (uhci_is_aspeed(uhci)) writel(val, uhci->regs + uhci_aspeed_reg(reg)); #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO else if (uhci_big_endian_mmio(uhci)) writew_be(val, uhci->regs + reg); #endif else writew(val, uhci->regs + reg); } static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) { if (uhci_has_pci_registers(uhci)) return UHCI_IN(inb(uhci->io_addr + reg)); else if (uhci_is_aspeed(uhci)) return readl(uhci->regs + uhci_aspeed_reg(reg)); #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO else if (uhci_big_endian_mmio(uhci)) return readb_be(uhci->regs + reg); #endif else return readb(uhci->regs + reg); } static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) { if (uhci_has_pci_registers(uhci)) UHCI_OUT(outb(val, uhci->io_addr + reg)); else if (uhci_is_aspeed(uhci)) writel(val, uhci->regs + uhci_aspeed_reg(reg)); #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO else if (uhci_big_endian_mmio(uhci)) writeb_be(val, uhci->regs + reg); #endif else writeb(val, uhci->regs + reg); } #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ #undef UHCI_IN #undef UHCI_OUT /* * The GRLIB GRUSBHC controller can use big endian format for its descriptors. * * UHCI controllers accessed through PCI work normally (little-endian * everywhere), so we don't bother supporting a BE-only mode. */ #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC #define uhci_big_endian_desc … /* cpu to uhci */ static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) { return uhci_big_endian_desc(uhci) ? (__force __hc32)cpu_to_be32(x) : (__force __hc32)cpu_to_le32(x); } /* uhci to cpu */ static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) { return uhci_big_endian_desc(uhci) ? be32_to_cpu((__force __be32)x) : le32_to_cpu((__force __le32)x); } #else /* cpu to uhci */ static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) { … } /* uhci to cpu */ static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) { … } #endif #endif
Codebase Browser
linux