// SPDX-License-Identifier: GPL-2.0 /* * xHCI host controller driver * * Copyright (C) 2008 Intel Corp. * * Author: Sarah Sharp * Some code borrowed from the Linux EHCI driver. */ #include <linux/slab.h> #include <asm/unaligned.h> #include <linux/bitfield.h> #include "xhci.h" #include "xhci-trace.h" #define PORT_WAKE_BITS … #define PORT_RWC_BITS … /* Default sublink speed attribute of each lane */ static u32 ssp_cap_default_ssa[] = …; static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf, u16 wLength) { … } static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, struct usb_hub_descriptor *desc, int ports) { … } /* Fill in the USB 2.0 roothub descriptor */ static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, struct usb_hub_descriptor *desc) { … } /* Fill in the USB 3.0 roothub descriptor */ static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, struct usb_hub_descriptor *desc) { … } static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, struct usb_hub_descriptor *desc) { … } static unsigned int xhci_port_speed(unsigned int port_status) { … } /* * These bits are Read Only (RO) and should be saved and written to the * registers: 0, 3, 10:13, 30 * connect status, over-current status, port speed, and device removable. * connect status and port speed are also sticky - meaning they're in * the AUX well and they aren't changed by a hot, warm, or cold reset. */ #define XHCI_PORT_RO … /* * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: * bits 5:8, 9, 14:15, 25:27 * link state, port power, port indicator state, "wake on" enable state */ #define XHCI_PORT_RWS … /* * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: * bit 4 (port reset) */ #define XHCI_PORT_RW1S … /* * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: * bits 1, 17, 18, 19, 20, 21, 22, 23 * port enable/disable, and * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), * over-current, reset, link state, and L1 change */ #define XHCI_PORT_RW1CS … /* * Bit 16 is RW, and writing a '1' to it causes the link state control to be * latched in */ #define XHCI_PORT_RW … /* * These bits are Reserved Zero (RsvdZ) and zero should be written to them: * bits 2, 24, 28:31 */ #define XHCI_PORT_RZ … /** * xhci_port_state_to_neutral() - Clean up read portsc value back into writeable * @state: u32 port value read from portsc register to be cleanup up * * Given a port state, this function returns a value that would result in the * port being in the same state, if the value was written to the port status * control register. * Save Read Only (RO) bits and save read/write bits where * writing a 0 clears the bit and writing a 1 sets the bit (RWS). * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. * * Return: u32 value that can be written back to portsc register without * changing port state. */ u32 xhci_port_state_to_neutral(u32 state) { … } EXPORT_SYMBOL_GPL(…); /* * Stop device * It issues stop endpoint command for EP 0 to 30. And wait the last command * to complete. * suspend will set to 1, if suspend bit need to set in command. */ static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) { … } /* * Ring device, it rings the all doorbells unconditionally. */ void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) { … } static void xhci_disable_port(struct xhci_hcd *xhci, struct xhci_port *port) { … } static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, u16 wIndex, __le32 __iomem *addr, u32 port_status) { … } struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd) { … } /* * xhci_set_port_power() must be called with xhci->lock held. * It will release and re-aquire the lock while calling ACPI * method. */ static void xhci_set_port_power(struct xhci_hcd *xhci, struct xhci_port *port, bool on, unsigned long *flags) __must_hold(&xhci->lock) { … } static void xhci_port_set_test_mode(struct xhci_hcd *xhci, u16 test_mode, u16 wIndex) { … } static int xhci_enter_test_mode(struct xhci_hcd *xhci, u16 test_mode, u16 wIndex, unsigned long *flags) __must_hold(&xhci->lock) { … } static int xhci_exit_test_mode(struct xhci_hcd *xhci) { … } void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, u32 link_state) { … } static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, struct xhci_port *port, u16 wake_mask) { … } /* Test and clear port RWC bit */ void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, u32 port_bit) { … } /* Updates Link Status for super Speed port */ static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, u32 *status, u32 status_reg) { … } /* * Function for Compliance Mode Quirk. * * This Function verifies if all xhc USB3 ports have entered U0, if so, * the compliance mode timer is deleted. A port won't enter * compliance mode if it has previously entered U0. */ static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex) { … } static int xhci_handle_usb2_port_link_resume(struct xhci_port *port, u32 portsc, unsigned long *flags) { … } static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) { … } static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status, u32 portsc) { … } static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status, u32 portsc, unsigned long *flags) { … } /* * Converts a raw xHCI port status into the format that external USB 2.0 or USB * 3.0 hubs use. * * Possible side effects: * - Mark a port as being done with device resume, * and ring the endpoint doorbells. * - Stop the Synopsys redriver Compliance Mode polling. * - Drop and reacquire the xHCI lock, in order to wait for port resume. */ static u32 xhci_get_port_status(struct usb_hcd *hcd, struct xhci_bus_state *bus_state, u16 wIndex, u32 raw_port_status, unsigned long *flags) __releases(&xhci->lock) __acquires(&xhci->lock) { … } int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength) { … } EXPORT_SYMBOL_GPL(…); /* * Returns 0 if the status hasn't changed, or the number of bytes in buf. * Ports are 0-indexed from the HCD point of view, * and 1-indexed from the USB core pointer of view. * * Note that the status change bits will be cleared as soon as a port status * change event is generated, so we use the saved status from that event. */ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) { … } #ifdef CONFIG_PM int xhci_bus_suspend(struct usb_hcd *hcd) { … } /* * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. * warm reset a USB3 device stuck in polling or compliance mode after resume. * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 */ static bool xhci_port_missing_cas_quirk(struct xhci_port *port) { … } int xhci_bus_resume(struct usb_hcd *hcd) { … } unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd) { … } #endif /* CONFIG_PM */