/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2015 MediaTek Inc. * Author: * Zhigang.Wei <[email protected]> * Chunfeng.Yun <[email protected]> */ #ifndef _XHCI_MTK_H_ #define _XHCI_MTK_H_ #include <linux/clk.h> #include <linux/hashtable.h> #include <linux/regulator/consumer.h> #include "xhci.h" #define BULK_CLKS_NUM … #define BULK_VREGS_NUM … /* support at most 64 ep, use 32 size hash table */ #define SCH_EP_HASH_BITS … /** * To simplify scheduler algorithm, set a upper limit for ESIT, * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT, * round down to the limit value, that means allocating more * bandwidth to it. */ #define XHCI_MTK_MAX_ESIT … #define XHCI_MTK_BW_INDEX(x) … #define UFRAMES_PER_FRAME … #define XHCI_MTK_FRAMES_CNT … /** * @fs_bus_bw_out: save bandwidth used by FS/LS OUT eps in each uframes * @fs_bus_bw_in: save bandwidth used by FS/LS IN eps in each uframes * @ls_bus_bw: save bandwidth used by LS eps in each uframes * @fs_frame_bw: save bandwidth used by FS/LS eps in each FS frames * @in_ss_cnt: the count of Start-Split for IN eps * @ep_list: Endpoints using this TT */ struct mu3h_sch_tt { … }; /** * struct mu3h_sch_bw_info: schedule information for bandwidth domain * * @bus_bw: array to keep track of bandwidth already used at each uframes * * treat a HS root port as a bandwidth domain, but treat a SS root port as * two bandwidth domains, one for IN eps and another for OUT eps. */ struct mu3h_sch_bw_info { … }; /** * struct mu3h_sch_ep_info: schedule information for endpoint * * @esit: unit is 125us, equal to 2 << Interval field in ep-context * @num_esit: number of @esit in a period * @num_budget_microframes: number of continuous uframes * (@repeat==1) scheduled within the interval * @hentry: hash table entry * @endpoint: linked into bandwidth domain which it belongs to * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to * @bw_info: bandwidth domain which this endpoint belongs * @sch_tt: mu3h_sch_tt linked into * @ep_type: endpoint type * @maxpkt: max packet size of endpoint * @ep: address of usb_host_endpoint struct * @allocated: the bandwidth is aready allocated from bus_bw * @offset: which uframe of the interval that transfer should be * scheduled first time within the interval * @repeat: the time gap between two uframes that transfers are * scheduled within a interval. in the simple algorithm, only * assign 0 or 1 to it; 0 means using only one uframe in a * interval, and 1 means using @num_budget_microframes * continuous uframes * @pkts: number of packets to be transferred in the scheduled uframes * @cs_count: number of CS that host will trigger * @burst_mode: burst mode for scheduling. 0: normal burst mode, * distribute the bMaxBurst+1 packets for a single burst * according to @pkts and @repeat, repeate the burst multiple * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets * according to @pkts and @repeat. normal mode is used by * default * @bw_budget_table: table to record bandwidth budget per microframe */ struct mu3h_sch_ep_info { … }; #define MU3C_U3_PORT_MAX … #define MU3C_U2_PORT_MAX … /** * struct mu3c_ippc_regs: MTK ssusb ip port control registers * @ip_pw_ctr0~3: ip power and clock control registers * @ip_pw_sts1~2: ip power and clock status registers * @ip_xhci_cap: ip xHCI capability register * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used * @u2_phy_pll: usb2 phy pll control register */ struct mu3c_ippc_regs { … }; struct xhci_hcd_mtk { … }; static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd) { … } int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk); void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk); int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); #endif /* _XHCI_MTK_H_ */
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