/* SPDX-License-Identifier: GPL-2.0 */ /* * SL811HS register declarations and HCD data structures * * Copyright (C) 2004 Psion Teklogix * Copyright (C) 2004 David Brownell * Copyright (C) 2001 Cypress Semiconductor Inc. */ /* * SL811HS has transfer registers, and control registers. In host/master * mode one set of registers is used; in peripheral/slave mode, another. * - SL11H only has some "A" transfer registers from 0x00-0x04 * - SL811HS also has "B" registers from 0x08-0x0c * - SL811S (or HS in slave mode) has four A+B sets, at 00, 10, 20, 30 */ #define SL811_EP_A(base) … #define SL811_EP_B(base) … #define SL811_HOST_BUF … #define SL811_PERIPH_EP0 … #define SL811_PERIPH_EP1 … #define SL811_PERIPH_EP2 … #define SL811_PERIPH_EP3 … /* TRANSFER REGISTERS: host and peripheral sides are similar * except for the control models (master vs slave). */ #define SL11H_HOSTCTLREG … #define SL11H_HCTLMASK_ARM … #define SL11H_HCTLMASK_ENABLE … #define SL11H_HCTLMASK_IN … #define SL11H_HCTLMASK_OUT … #define SL11H_HCTLMASK_ISOCH … #define SL11H_HCTLMASK_AFTERSOF … #define SL11H_HCTLMASK_TOGGLE … #define SL11H_HCTLMASK_PREAMBLE … #define SL11H_BUFADDRREG … #define SL11H_BUFLNTHREG … #define SL11H_PKTSTATREG … #define SL11H_STATMASK_ACK … #define SL11H_STATMASK_ERROR … #define SL11H_STATMASK_TMOUT … #define SL11H_STATMASK_SEQ … #define SL11H_STATMASK_SETUP … #define SL11H_STATMASK_OVF … #define SL11H_STATMASK_NAK … #define SL11H_STATMASK_STALL … #define SL11H_PIDEPREG … #define SL_SETUP … #define SL_IN … #define SL_OUT … #define SL_SOF … #define SL_PREAMBLE … #define SL_NAK … #define SL_STALL … #define SL_DATA0 … #define SL_DATA1 … #define SL11H_XFERCNTREG … #define SL11H_DEVADDRREG … /* CONTROL REGISTERS: host and peripheral are very different. */ #define SL11H_CTLREG1 … #define SL11H_CTL1MASK_SOF_ENA … #define SL11H_CTL1MASK_FORCE … #define SL11H_CTL1MASK_NORMAL … #define SL11H_CTL1MASK_SE0 … #define SL11H_CTL1MASK_J … #define SL11H_CTL1MASK_K … #define SL11H_CTL1MASK_LSPD … #define SL11H_CTL1MASK_SUSPEND … #define SL11H_IRQ_ENABLE … #define SL11H_INTMASK_DONE_A … #define SL11H_INTMASK_DONE_B … #define SL11H_INTMASK_SOFINTR … #define SL11H_INTMASK_INSRMV … #define SL11H_INTMASK_RD … #define SL11H_INTMASK_DP … #define SL11S_ADDRESS … /* 0x08-0x0c are for the B buffer (not in SL11) */ #define SL11H_IRQ_STATUS … #define SL11H_HWREVREG … #define SL11H_HWRMASK_HWREV … #define SL11H_SOFLOWREG … #define SL11H_SOFTMRREG … /* a write to this register enables SL811HS features. * HOST flag presumably overrides the chip input signal? */ #define SL811HS_CTLREG2 … #define SL811HS_CTL2MASK_SOF_MASK … #define SL811HS_CTL2MASK_DSWAP … #define SL811HS_CTL2MASK_HOST … #define SL811HS_CTL2_INIT … /* DATA BUFFERS: registers from 0x10..0xff are for data buffers; * that's 240 bytes, which we'll split evenly between A and B sides. * Only ISO can use more than 64 bytes per packet. * (The SL11S has 0x40..0xff for buffers.) */ #define H_MAXPACKET … #define SL11H_DATA_START … #define SL811HS_PACKET_BUF(is_a) … /*-------------------------------------------------------------------------*/ #define LOG2_PERIODIC_SIZE … #define PERIODIC_SIZE … struct sl811 { … }; static inline struct sl811 *hcd_to_sl811(struct usb_hcd *hcd) { … } static inline struct usb_hcd *sl811_to_hcd(struct sl811 *sl811) { … } struct sl811h_ep { … }; /*-------------------------------------------------------------------------*/ /* These register utilities should work for the SL811S register API too * NOTE: caller must hold sl811->lock. */ static inline u8 sl811_read(struct sl811 *sl811, int reg) { … } static inline void sl811_write(struct sl811 *sl811, int reg, u8 val) { … } static inline void sl811_write_buf(struct sl811 *sl811, int addr, const void *buf, size_t count) { … } static inline void sl811_read_buf(struct sl811 *sl811, int addr, void *buf, size_t count) { … } /*-------------------------------------------------------------------------*/ #ifdef PACKET_TRACE #define PACKET … #else #define PACKET(stuff...) … #endif
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