/* SPDX-License-Identifier: GPL-2.0+ */ /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc. * Copyright (c) 2005 MontaVista Software */ #ifndef _EHCI_FSL_H #define _EHCI_FSL_H /* offsets for the non-ehci registers in the FSL SOC USB controller */ #define FSL_SOC_USB_SBUSCFG … #define SBUSCFG_INCR8 … #define FSL_SOC_USB_ULPIVP … #define FSL_SOC_USB_PORTSC1 … #define PORT_PTS_MSK … #define PORT_PTS_UTMI … #define PORT_PTS_ULPI … #define PORT_PTS_SERIAL … #define PORT_PTS_PTW … #define FSL_SOC_USB_PORTSC2 … #define FSL_SOC_USB_USBMODE … #define USBMODE_CM_MASK … #define USBMODE_CM_HOST … #define USBMODE_ES … #define FSL_SOC_USB_USBGENCTRL … #define USBGENCTRL_PPP … #define USBGENCTRL_PFP … #define FSL_SOC_USB_ISIPHYCTRL … #define ISIPHYCTRL_PXE … #define ISIPHYCTRL_PHYE … #define FSL_SOC_USB_SNOOP1 … #define FSL_SOC_USB_SNOOP2 … #define FSL_SOC_USB_AGECNTTHRSH … #define FSL_SOC_USB_PRICTRL … #define FSL_SOC_USB_SICTRL … #define FSL_SOC_USB_CTRL … #define CTRL_UTMI_PHY_EN … #define CTRL_PHY_CLK_VALID … #define SNOOP_SIZE_2GB … /* control Register Bit Masks */ #define CONTROL_REGISTER_W1C_MASK … #define ULPI_INT_EN … #define WU_INT_EN … #define USB_CTRL_USB_EN … #define LINE_STATE_FILTER__EN … #define KEEP_OTG_ON … #define OTG_PORT … #define PLL_RESET … #define UTMI_PHY_EN … #define ULPI_PHY_CLK_SEL … #define PHY_CLK_VALID … /* Retry count for checking UTMI PHY CLK validity */ #define UTMI_PHY_CLK_VALID_CHK_RETRY … #endif /* _EHCI_FSL_H */
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