linux/drivers/usb/c67x00/c67x00-ll-hpi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * c67x00-ll-hpi.c: Cypress C67X00 USB Low level interface using HPI
 *
 * Copyright (C) 2006-2008 Barco N.V.
 *    Derived from the Cypress cy7c67200/300 ezusb linux driver and
 *    based on multiple host controller drivers inside the linux kernel.
 */

#include <asm/byteorder.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/usb/c67x00.h>
#include "c67x00.h"

#define COMM_REGS …

struct c67x00_lcp_int_data { … };

/* -------------------------------------------------------------------------- */
/* Interface definitions */

#define COMM_ACK …
#define COMM_NAK …

#define COMM_RESET …
#define COMM_EXEC_INT …
#define COMM_INT_NUM …

/* Registers 0 to COMM_REGS-1 */
#define COMM_R(x) …

#define HUSB_SIE_pCurrentTDPtr(x) …
#define HUSB_SIE_pTDListDone_Sem(x) …
#define HUSB_pEOT …

/* Software interrupts */
/* 114, 115: */
#define HUSB_SIE_INIT_INT(x) …
#define HUSB_RESET_INT …

#define SUSB_INIT_INT …
#define SUSB_INIT_INT_LOC …

/* -----------------------------------------------------------------------
 * HPI implementation
 *
 * The c67x00 chip also support control via SPI or HSS serial
 * interfaces. However, this driver assumes that register access can
 * be performed from IRQ context. While this is a safe assumption with
 * the HPI interface, it is not true for the serial interfaces.
 */

/* HPI registers */
#define HPI_DATA …
#define HPI_MAILBOX …
#define HPI_ADDR …
#define HPI_STATUS …

/*
 * According to CY7C67300 specification (tables 140 and 141) HPI read and
 * write cycle duration Tcyc must be at least 6T long, where T is 1/48MHz,
 * which is 125ns.
 */
#define HPI_T_CYC_NS …

static inline u16 hpi_read_reg(struct c67x00_device *dev, int reg)
{ … }

static inline void hpi_write_reg(struct c67x00_device *dev, int reg, u16 value)
{ … }

static inline u16 hpi_read_word_nolock(struct c67x00_device *dev, u16 reg)
{ … }

static u16 hpi_read_word(struct c67x00_device *dev, u16 reg)
{ … }

static void hpi_write_word_nolock(struct c67x00_device *dev, u16 reg, u16 value)
{ … }

static void hpi_write_word(struct c67x00_device *dev, u16 reg, u16 value)
{ … }

/*
 * Only data is little endian, addr has cpu endianess
 */
static void hpi_write_words_le16(struct c67x00_device *dev, u16 addr,
				 __le16 *data, u16 count)
{ … }

/*
 * Only data is little endian, addr has cpu endianess
 */
static void hpi_read_words_le16(struct c67x00_device *dev, u16 addr,
				__le16 *data, u16 count)
{ … }

static void hpi_set_bits(struct c67x00_device *dev, u16 reg, u16 mask)
{ … }

static void hpi_clear_bits(struct c67x00_device *dev, u16 reg, u16 mask)
{ … }

static u16 hpi_recv_mbox(struct c67x00_device *dev)
{ … }

static u16 hpi_send_mbox(struct c67x00_device *dev, u16 value)
{ … }

u16 c67x00_ll_hpi_status(struct c67x00_device *dev)
{ … }

void c67x00_ll_hpi_reg_init(struct c67x00_device *dev)
{ … }

void c67x00_ll_hpi_enable_sofeop(struct c67x00_sie *sie)
{ … }

void c67x00_ll_hpi_disable_sofeop(struct c67x00_sie *sie)
{ … }

/* -------------------------------------------------------------------------- */
/* Transactions */

static inline int ll_recv_msg(struct c67x00_device *dev)
{ … }

/* -------------------------------------------------------------------------- */
/* General functions */

u16 c67x00_ll_fetch_siemsg(struct c67x00_device *dev, int sie_num)
{ … }

u16 c67x00_ll_get_usb_ctl(struct c67x00_sie *sie)
{ … }

/*
 * c67x00_ll_usb_clear_status - clear the USB status bits
 */
void c67x00_ll_usb_clear_status(struct c67x00_sie *sie, u16 bits)
{ … }

u16 c67x00_ll_usb_get_status(struct c67x00_sie *sie)
{ … }

/* -------------------------------------------------------------------------- */

static int c67x00_comm_exec_int(struct c67x00_device *dev, u16 nr,
				struct c67x00_lcp_int_data *data)
{ … }

/* -------------------------------------------------------------------------- */
/* Host specific functions */

void c67x00_ll_set_husb_eot(struct c67x00_device *dev, u16 value)
{ … }

static inline void c67x00_ll_husb_sie_init(struct c67x00_sie *sie)
{ … }

void c67x00_ll_husb_reset(struct c67x00_sie *sie, int port)
{ … }

void c67x00_ll_husb_set_current_td(struct c67x00_sie *sie, u16 addr)
{ … }

u16 c67x00_ll_husb_get_current_td(struct c67x00_sie *sie)
{ … }

u16 c67x00_ll_husb_get_frame(struct c67x00_sie *sie)
{ … }

void c67x00_ll_husb_init_host_port(struct c67x00_sie *sie)
{ … }

void c67x00_ll_husb_reset_port(struct c67x00_sie *sie, int port)
{ … }

/* -------------------------------------------------------------------------- */

void c67x00_ll_irq(struct c67x00_device *dev, u16 int_status)
{ … }

/* -------------------------------------------------------------------------- */

int c67x00_ll_reset(struct c67x00_device *dev)
{ … }

/* -------------------------------------------------------------------------- */

/*
 * c67x00_ll_write_mem_le16 - write into c67x00 memory
 * Only data is little endian, addr has cpu endianess.
 */
void c67x00_ll_write_mem_le16(struct c67x00_device *dev, u16 addr,
			      void *data, int len)
{ … }

/*
 * c67x00_ll_read_mem_le16 - read from c67x00 memory
 * Only data is little endian, addr has cpu endianess.
 */
void c67x00_ll_read_mem_le16(struct c67x00_device *dev, u16 addr,
			     void *data, int len)
{ … }

/* -------------------------------------------------------------------------- */

void c67x00_ll_init(struct c67x00_device *dev)
{ … }

void c67x00_ll_release(struct c67x00_device *dev)
{ … }